• 한국정밀공학회지
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• 제15권1호
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• pp.51-59
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• 1998

The purposes of the paper are to consider the failure phenomenon based on delamination and crack when the encapsulant of plastic IC package under hygrothermal loading in the IR soldering process is on elastic and viscoelastic behavior due to the temperature and to show the optimum design using fracture mechanics. The model for analysis is the plastic SOJ package with a dimpled diepad. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance to fracture by calculating J-integrals in low temperature and C(t)-integrals in high temperature with the change of the design under hygrothermal loading. The optimum design to depress the delamination and crack in the plastic IC package is presented.

• 한국정밀공학회지
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• 제15권1호
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• pp.43-50
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• 1998

The purpose of the paper is to protect the damage of plastic IC package with searching the cause of the fracture due to the delamination and crack when the encapsulant of plastic IC package is on viscoelastic behavior with the effect of creep on high temperature, The model for analysis is the plastic SOJ package with dimpled diepad in the IR soldering process of surface mounting technology. The risk of delamination with calculating the distribution of viscoelastic thermal stress in the package without the crack in the surface mounting process is checked. The package model with the perfect delamination between chip and diepad is chosen to estimate the resistance against fracture in thermal loading with calculating C (t)-integrals according to the change of the design. The optimum design to depress the delamination and crack is presented.

• Journal of Mechanical Science and Technology
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• 제18권3호
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• pp.357-369
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• 2004

The purposes of the paper are to analyze the fracture phenomenon by delamination and cracking when the encapsulant of plastic IC package with polyimide coating shows viscoelastic behavior under hygrothermal loading in the IR soldering process and to suggest more reliable design conditions by the approaches of stress analysis and fracture mechanics. The model is the plastic SOJ package with the polyimide coating surrounding chip and dimpled diepad. On the package without cracks, the optimum position and thickness of polyimide coating to decrease the maximum differences of strains at the bonding surfaces of parts of the package are studied. For the model delaminated fully between the chip and the dimpled diepad, C(t)-integral values are calculated for the various design variables. Finally, the optimal values of design variables to depress the delamination and crack growth in the plastic IC package are obtained.

• 대한기계학회논문집A
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• 제20권4호
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• pp.1347-1355
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• 1996

The purpose of this paper is to evaluate the delamination and fracture integrity of the IC plastic package under hygrothermal loading by stress analysis and fracture mechanics approaches. The plastic SOJ package with a dimpled diepad under the reflow slodering process of IR heating type is considered. On the package without a crack, the stress variation according to the change of the design variables such as the material and shape of the package is calculated and the possibility of delamination is considered. For the model fully delaminated between the chip and diepad, J-integrals are calculated for the various design variables and the fracture integrity is discussed. From the results, optimal design values of variables to prevent the delamination and fracture of IC package are obtained. In this study, FDM program to obtain the vapor pressure from the content of moisture absorbed into the package is developed.

• 전자공학회논문지D
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• 제35D권4호
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• pp.61-70
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• 1998

The electrical performance of a package is extremely important for high speed digital system operations. CSP(chip scale package) is known to have better electrical performance than the convnetional packages. In this paper, the electrical performance of the BLP(bottom leaded plastic) package, a kind of CSP, has been alayzed by both simulation and real measurement. The electrical perfdormance of a BLP was compared with that of the conventioanl TSOP(thin small outline package). The leadinductanceand lead capacitance were used for the comparison purposes. The new BLP design provides much better electrical performance that TSOP package. It has about 40% favorable parameter values.

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.57-60
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• 2015

Electric power in large devices is controlled by digital circuits, such as switching mode power supply. This kind of power circuits require accurate current sensor for power distribution. We studied characteristics of shunt resistor, which has many advantages for commercial application compared to Hall-effect current sensor. We applied ceramic package to the shunt resistor. Ceramic package has good thermal conductivity compared to plastic package, and this point is important for space requirement in Printed Circuit Board (PCB). Another advantage of the ceramic package is that surface mount technology (SMT) can be used for production. Our experimental results showed that the ceramic packaged resistor showed about 50% lower temperature than the plastic packaged one. Burning point and frequency characteristics are also discussed.

• 한국재료학회지
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• 제19권5호
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.

• 한국산업융합학회 논문집
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• 제2권2호
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• pp.131-137
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• 1999

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

• 대한기계학회논문집
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• 제18권3호
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• pp.729-737
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• 1994

A three-dimensional finite element model of a 20-pin plastic dual-in-line package(PDIP) plugged into a PCE has been developed by using the finite element code ANSYS. The model has been used for thermal characterization of the package during its normal operation under natural convection cooling. Temperature distributions in the package and PCB are obtained from numerical analysis and compared with experimentally measured data. Various cases are assumed and analyzed to study the effects of package and PCB materials on thermal characteristics of PDIP with and without aluminum heatspreader. Thermal dissipation capability of PDIP is greatly increased due to copper die pad/lead frame and heatspreader. However, thermally induced stresses in the package and fatigue life of chip are improved for PDIP with Alloy 42 die pad/lead frame and no heatspreader. It is also found that the role of PCB on thermal characteristics of PDIP is very imporatant.

• 대한기계학회논문집A
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• 제28권6호
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• pp.709-716
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• 2004

In order to prevent the interface delamination of an plastic IC package in the infrared (IR) soldering process, we tried to reduce stress by parameterization, sensitivity analysis and unconstraint optimization. The design variables of dimensions and material properties are determined among all the possible variables from the parametric study. Their optimized values are determined by applying the unconstraint optimization to the parameterized IC package. The maximum von-Mises stress value decreases greatly by optimum design.