• ETRI Journal
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• 제30권3호
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• 한국정보통신학회논문지
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• 제8권3호
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• pp.570-576
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• 2004

본 논문에서는 고속 무선 LAN에서 사용하는 IEEE 802.11a OFDM(Orthogonal Frequency Division Multiplexing)에서 주요 구성인 IFFT/FFT(Inverse Fast Fourier Transform/Fast Fourier Transform)에 대한 설계에 대해 비교하였다. 설계된 IFFT/FFT는 무선 LAN의 표준에 맞게 64 point의 FFT로 연산을 수행하며, S/P(Serial-to-Parallel)이나 P/S(Parallel-to-Serial)변환기가 필요 없는 Pipelined FFT의 구조로 설계하였다. 그 중 Radix-2 알고리즘을 이용한 R22SDF(Radix-2 Single-path Delay Feedback) 방식, R2SDF(Radix-2 Single-path Delay Feedback) 방식과 Radix-4 알고리즘을 이용한 R4SDF(Radix-4 Single-path Delay Feedback) 방식, R4SDC(Radix-4 Single-path Delay Commutator) 방식을 사용하여 비교하였다. 하드웨어 구현 시 발생하는 오차를 줄이기 위해 Butterfly 연산 후 일부 소수점을 가지고 계산하는 구조로 설계하였다. R22SDF 방식을 이용할 경우 메모리를 제외한 전체 게이트 수가 44,747 개로 다른 구조에 비해 적은 하드웨어와 낮은 오차율을 가진다.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• 한국정보전자통신기술학회논문지
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• 제11권3호
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• 전기학회논문지
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• 제56권4호
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• pp.790-794
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• 2007

This paper presents a new index mapping method for DFT (Discrete Fourier Transform) and its application to multidimensional DFT. Unlike conventional index mapping methods such as DIT (Decimation in Time) or DIF (Decimation in Frequency) algorithms, the proposed method is based on two levels of decomposition and it can be very efficiently used for implementing multidimensional DFT as well as 1-dimensional DFT. The proposed pipelined architecture for multidimensional DFT is very flexible so that it can lead to the best tradeoff between performance and hardware requirements. Also, it can be easily extended to higher dimensional DFTs since the number of CEs (Computational Elements) and DCs (Delay Commutators) increase only linearly with the dimension. Various implementation options based on different radices and different pipelining depths will be presented.

• 대한전자공학회논문지SD
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• 제39권5호
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• pp.65-73
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• 2002

본 논문에서는 순차적 입력 데이터 처리방식을 이용하여 2048 point FFT/IFFT를 단일 칩으로 구현하는 방법을 제안하고 검증하였다. 순차적으로 입력되는 2028개의 복소 데이터를 처리하기 위해서는 입력 데이터를 저장하는 버퍼가 필요하고 이 입력 버퍼로는 DRAM 회로를 이용한 지연 변환기 (delay commutator)를 사용하여 전체 칩 면적을 35% 이상 줄일 수 있었다. 전체 FFT/IFFT는 16 point FFT를 기본 블록으로 사용하며, radix-4 구조를 가지는 다섯 단계와 radix-2 구조를 가지는 하나의 단계로 이루어져 있다. 각 단계마다 연산을 수행하면서 증가되는 결과 S/N 비를 유지하면서 비트 라운딩을 하기 위해 convergent block floating point (CBFP) 알고리즘을 적용하여 digital audio broadcasting(DAB)을 위한 단일 칩 설계에 기여하였다.

• 대한의용생체공학회:의공학회지
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• 제6권2호
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• 대한의용생체공학회:의공학회지
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• 제6권2호
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• 대한전자공학회논문지SD
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• 제40권5호
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• pp.312-320
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• 2003

본 논문에서는 고속 평판 디스플레이 응용을 위한 8b 200 MHz 0.18 um CMOS A/D 변환기 (Analog-to-Digital Converter:ADC)를 제안한다. 제안하는 A/D 변환기는 200 MHz의 샘플링 클럭 속도에서 샘플링 클럭 속도보다 더 높은 입력 대역폭을 얻기 위해서 개선된 bootstrapping 기법을 사용한다. Bootstrapping 기법이 적용된 샘플-앤-흘드 증폭기(Sample-and-Hold Amplifier. SHA)는 기존의 회로 보다 향상된 정확도를 가지며, 1.7 V의 전원 전압, 200 MHz의 샘플링 클럭, 500 MHz의 정현파 입력에서 SHA의 출력을 FFT(Fast Fourier Transform) 분석한 결과 7.2 비트의 유효 비트 수(effective number of bits)를 나타내었다. 또한 병합 캐패시터 스위칭 (Merged-Capacitor Switching:MCS) 기법을 사용하여 기존의 A/D 변환기에 사용되는 캐패시터의 숫자를 50 % 줄임으로써 샘플링 속도를 높임과 동시에 면적을 최소화하였다. 제안하는 40 변환기는 0.18 um n-well single-poly quad-metal CMOS 공정을 사용하여 모의 실험 되었으며, 1.7 V 전원 전압, 200 MHz의 샘플링 클럭에서 73 mW의 전력을 소모한다.