• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.843-844
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.05a
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• pp.855-856
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• 2010

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.176-179
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• 1989

The optimization of the monolithic pin-FET receiver is discussed, with emphasis on the sensitivity and bandwidth. The amplifier circuit, bias resistance, total input capacitance, and transconductance of FET for the 2 Gbps transmission are calculated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.625-629
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• 2003

Low loss and high power MMIC limiters with GaAs PM diode were designed and fabricated. The new epitaxial structure of GaAs PIN diode was proposed in order to increase the high power capability. 2 types of limiter circuits have been designed and the limiting powers have been measured. Results indicated that the limiting power was depended on the circuit topology. Limiting power levels of 2-stage limiters are measured 16 ㏈m and 22 ㏈m at 14 ㎓, respectively.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1668-1669
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• 2011

본 논문에서는 Pogo Pin의 신호 전달 특성을 Ansys사의 Full wave simulation tool(HFSS)를 사용하여 분석하였고, 측정을 위해서 필요한 interface(Guide PCB)의 특성은 2-port de-embedding 방법을 이용하여 제거하였다. Guide PCB의 특성이 제거된 Pogo Pin만의 시뮬레이션 결과와 circuit simulator인 Agilent사의 ADS를 사용하여 Guide PCB의 특성을 de-embedding한 결과를 비교 검증하였고, Pogo Pin의 시뮬레이션 결과와 PCB의 특성을 de-embedding한 결과가 0~8 GHz까지 일치하는 것을 확인하였다.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.34-39
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• 2009

Four-digit PIN(Personal Identification Number) is a well-known user authentication method used for many applications including ATMs and mobile phones. However, it is vulnerable to shoulder surfing attacks(SSAs). In this paper, we present new PIN entry methods which are secure against SSA and easy to use. We compare the usability and security of these methods with those of the existing methods.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.3
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• pp.105-109
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• 2017

In this paper is proposed wide band reconfiguration antenna by using PIN diode. The proposed antenna consisted of elliptical dipole and exponential taper balun. The proposed new matching method was exponential tapered balun in this paper. The research paper comprised of two PIN diode and Elliptical dipole. This paper used CPW to CPS feed. We obtained a good band width characteristics result by simulating. This antenna is designed to apply ISM and WiFi band.

• Proceedings of the KAIS Fall Conference
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• 2009.12a
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• pp.949-952
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• 2009

인터넷 서비스를 사용하기 위해서 사용자들은 이름과 주민등록번호로 실명 인증을 받은 후에 ID를 부여 받았으나, 최근 보안상 문제로 주민등록번호 대체 수단인 I-PIN 서비스를 사용하고 있다. 그리고 하나의 ID로 통합하여 인터넷 서비스를 받을 수 있는 OpenID 서비스가 국내에서도 시행중이지만 사용자 인증이 없어 악성 댓글과 스팸 등으로 악용될 수 있으며 피싱에 대한 문제점을 지적하고 있다. 본 논문에서는 OpenID에서 회원가입을 할 때 I-PIN을 사용하여 사용자 인증을 하는 기법을 제안하고 악의적인 IDP와 RP의 피싱 문제점을 보안하였다. 기존의 OpenID와 I-PIN을 적용한 OpenID를 비교분석을 통하여 보안적인 측면이 강화된 것을 확인할 수 있으며 피싱에 안전하도록 설계하였다.

• Transactions of Materials Processing
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• v.15 no.1 s.82
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• pp.42-46
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• 2006

For mass production, usually injection mold has multi-cavity which is filled through geometrical balanced runner system. Despite geometrical balanced runner system, filling imbalances between cavity to cavity have always been observed. These filling imbalances are one of the most significant factors to affect quality of plastic parts. Filling imbalances are results from non-symmetrical shear rate distribution within melt when it flows through tile runner system. It has been possible to decrease filling imbalance by optimizing processing conditions, but it has not completely eliminated this phenomenon during injection molding processing. This paper presents a solution for these filling imbalances by using Runner Core pin (RC pin). The Runner Core pin which is developed in this study creates a symmetrical shear distribution within runner. As a result of using Runner Core pin, a remarkable improvement in reducing filling imbalances was confirmed.