• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권4호
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of IKEEE
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• 제23권3호
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제10권5호
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• pp.653-662
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• 1999

In this paper, subharmonically injection locked oscillator(SILO) was designed and measured. SILO with series feedback was designed using Two Signal Method(TSM). The free-running oscillator frequency was 9.4 GHz with 6 dBm output power. In case of injection, the multiplied injected signal locked the free-running frequency. The locked signal output power was higher than any other spurious response at least 40 dB. The locking range was 220MHz (second subharmonic locking), 100 MHz(4th subharmonic locking), and phase noise was -111 dBc/Hz, -104 dBc/Hz at 100kHz offset, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제7권5호
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• pp.1076-1081
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• 2003

A new technique for generating millimeter-wave signals from a semiconductor laser is presented. The method multiples the signal frequency by using optical injection of short optical pulses at a sub-harmonic of the cavity round-trip frequency to drive the laser oscillating at its resonant frequency. A 32GHz signal is generated using a multisection semiconductor laser operated under continuous wave conditions, by injection optical pulses at a repetition rate equal to the fourth subhamonic(8GHz). The generated millimeter-wave signal exhibits a large submamonic suppression ratio(＞17 dB), large frequency detuning range (>300 MHz) low levels of phase-noise(-77.5 dBc/Hz), and large locking (>400 MHz)

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제45권5호
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권11호
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제15권2호
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2010년도 추계학술대회 논문집
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• pp.339-340
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• 2010

• Proceedings of the IEEK Conference
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.