• Proceedings of the KIEE Conference
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• 1999.07a
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• pp.64-66
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• 1999

Switched reluctance motor(SRM) has the advantages of simple structure, low rotor inertia and high efficiency. However, position sensor is essential in SRM in order to synchronize the phase excitation to the rotor position. The position sensors increase the cost of drive system and tend to reduce system reliability. This paper investigates the speed control of sensorless SRM in which the phase current and change rate are utilized in position decision, and the period of dwell angle is variable by compensating the rotor angle. The proposed system consists of position decision, phase locked loop controller, switching angle controller and inverter. The performances in the proposed system are verified through experiments.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.684-686
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• 2000

Switched reluctance motor(SRM) has the advantages of simple structure, low rotor inertia. and high efficiency. However position sensor is essential in SRM in order to synchronize the phase excitation to the rotor position. The position sensors increase the cost of drive system and tend to reduce system reliability. This paper investigates the speed control of sensorless SRM in which the phase current and change rate are utilized in position decision, and the period of dwell angle is variable by compensating the rotor angle for speed control. The proposed system consists of position decision. phase locked loop controller, switching angle controller and inverter. The performances in the proposed system are verified through the experiment.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.45-53
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• 2007

To recover transmitted signal perfectly at DTV receiver, we have to acquire carrier frequency synchronization to compensate pilot signal which located in wrong position and rotated phase. Also, we need a symbol timing synchronization to compensate sampling timing error. Conventionally, to synchronize symbol timing, we use Gardner's scheme which used in multi-level signal. Gardner's scheme is well known for its sampling the timing error signal from every symbol and it makes easy to detect and keep timing sync in multi-path channel. In this paper, to discuss the problem when the received power level is out of range and we cannot get synchronization information. With this problem, we use 2 step procedures. First, we put a received signal power compensation block before Garder's timing error detector. Second, adaptive loop filter to get a fast synchronization information and averaging loop filter's output value to reduce the amount of jitter after synchronization in PLL(Phased Locked Loop) circuit which is used to get a carrier frequency synchronization and symbol timing synchronization. Using the averaging value, we can estimate offset. Based on offset changing ratio, we can adapt adaptive loop filter to carrier frequency and symbol timing synchronization circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.10-17
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• 2012

This paper presents a clock regenerator using two $2^{nd}$ order ${\sum}-{\Delta}$ (sigma-delta) modulators for wide range of dividing ratio as defined in HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. By converting the integer and decimal part of the N and CTS values in HDMI format and processing separately at two different ${\sum}-{\Delta}$ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard. The circuit is fabricated using 0.18 ${\mu}m$ CMOS and shows 13 mW power consumption with an on-chip loop filter implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3069-3085
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• 1996

This paper shows an accurate charge-pump PLL model which considers the wave-form distortion in high speed operation of charge-pump PLL, the leakage current in loop filter, and a physical limit in charge-pump. With proposed model of charge-pump PLL, overload and stability are derived theoretically and the results are compared to the conventional model. Unlike the ideal charge-pump PLL that simplifies calculations, it is possible to analyze the transient-state and the steady-state at the same time with proposed accurate model. Thus, charge-pump over load, in the transient-state and the stead-state of charge-pump, is accuragely analyzed and the results are confirmed with simulation.

• Korean Journal of Optics and Photonics
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• v.11 no.5
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• pp.330-334
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• 2000

A new pha~e lock loop (PLL) IS proposed and demonstrated fat clock recovery from 40 Gblt/s time-dIvision-multiplexed (TDM) optical pulse tri.lin, The proposed clock lecovery scheme lmproves the Jitter effecl cOlmng from the clock. pulse laser of harmonically-mode locked flber laser The cross-corrdation frequency component between the optical Signa] and an optical clock pulse tram is deteCled as a fonr-wave-mixing (FWM) SIgnal generated in SOA. The lock-in freqnency range of the clod. recovery IS found to be within 10 KHz. 0 KHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Journal of Electrical Engineering and Technology
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• v.6 no.5
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• pp.658-665
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• 2011

In the present paper, a novel fast peak detector for single- or three-phase unsymmetrical voltage sags is proposed. The proposed detector is modified from a single-phase digital phase-locked loop based on a d-q transformation using an all-pass filter (APF). APF generates a virtual phase with $90^{\circ}$ phase delay. However, this virtual phase cannot reflect a sudden change of the grid voltage in the moment of voltage sag, which causes a peak value to be significantly distorted and to settle down slowly. Specifically, the settling time of the peak value is too long when voltage sag occurs around a zero crossing, such as phase $0^{\circ}$ and $180^{\circ}$. This paper describes the operating principle of the APF problem and proposes a modified all-pass filter (MAPF) to mitigate the inherent APF problem. In addition, a new fast peak detector using MAPF is proposed. The proposed detector is able to calculate a peak value within 0.5 ms, even when voltage sag occurs around zero crossing. The proposed fast peak detector is compared with the conventional detector using APF. Results show that the proposed detector has faster detection time in the whole phase range. Furthermore, the proposed fast peak detector can be effectively applied to unsymmetrical three-phase voltage sags. Simulation and experimental results verify the advantages of the proposed detector and MAPF.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1110-1121
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• 2016

The mathematical model of a three phase PWM converter under the stationary αβ reference frame is deduced and constructed based on a Proportional-Resonant (PR) regulator, which can replace trigonometric function calculation, Park transformation, real-time detection of a Phase Locked Loop and feed-forward decoupling with the proposed accurate calculation of the inductance voltage vector. To avoid the parallel resonance of the LCL topology, the active damping method of the proportional capacitor-current feedback is employed. As to current vector error elimination, an optimized PR controller of the inner current loop is proposed with the zero-pole matching (ZPM) and cancellation method to configure the regulator. The impacts on system's characteristics and stability margin caused by the PR controller and control parameter variations in the inner-current loop are analyzed, and the correlations among active damping feedback coefficient, sampling and transport delay, and system robustness have been established. An equivalent model of the inner current loop is studied via the pole-zero locus along with the pole placement method and frequency response characteristics. Then, the parameter values of the control system are chosen according to their decisive roles and performance indicators. Finally, simulation and experimental results obtained while adopting the proposed method illustrated its feasibility and effectiveness, and the inner current loop achieved zero static error tracking with a good dynamic response and steady-state performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2716-2724
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• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.