• Title/Summary/Keyword: parasitic capacitance of source-drain

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The Fabrication of a-Si:H TFT Improving Parasitic Capacitance of Source-Drain (소오스-드레인 기생용량을 개선한 박막트랜지스터 제조공정)

  • 허창우
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.821-825
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    • 2004
  • The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ), a-Si:H(2000 ) and n+a-Si:H (500). We have deposited n+a-Si:H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

A Study on Improvement of a-Si:H TFT Operating Speed

  • Hur, Chang-Wu
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.42-44
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    • 2007
  • The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

  • An, TaeYoon;Choe, KyeongKeun;Kwon, Kee-Won;Kim, SoYoung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.525-536
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    • 2014
  • Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

Decrease of Parasitic Capacitance for Improvement of RF Performance of Multi-finger MOSFETs in 90-nm CMOS Technology

  • Jang, Seong-Yong;Kwon, Sung-Kyu;Shin, Jong-Kwan;Yu, Jae-Nam;Oh, Sun-Ho;Jeong, Jin-Woong;Song, Hyeong-Sub;Kim, Choul-Young;Lee, Ga-Won;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.2
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    • pp.312-317
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    • 2015
  • In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

Circuit Performance Prediction of Scaled FinFET Following ITRS Roadmap based on Accurate Parasitic Compact Model (정확한 기생 성분을 고려한 ITRS roadmap 기반 FinFET 공정 노드별 회로 성능 예측)

  • Choe, KyeungKeun;Kwon, Kee-Won;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.10
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    • pp.33-46
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    • 2015
  • In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

Development of a 2.14-GHz High Efficiency Class-F Power Amplifier (2.14-GHz 대역 고효율 Class-F 전력 증폭기 개발)

  • Kim, Jung-Joon;Moon, Jung-Hwan;Kim, Jang-Heon;Kim, Il-Du;Jun, Myoung-Su;Kim, Bum-Man
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.873-879
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    • 2007
  • We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the $2^{nd}\;and\;3^{rd}$ harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.

A Novel External Resistance Method for Extraction of Accurate Effective Channel Carrier Mobility and Separated Parasitic Source/Drain Resistances in Submicron n-channel LDD MOSFET's (새로운 ERM-방법에 의한 미세구조 N-채널 MOSFET의 유효 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출)

  • Kim, Hyun-Chang;Cho, Su-Dong;Song, Sang-Jun;Kim, Dea-Jeong;Kim, Dong-Myong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.1-9
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    • 2000
  • A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

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Mixed-mode simulation of transient characteristics of 4H-SiC DMOSFETs (Mixed-mode simulation을 이용한 4H-SiC DMOSFETs의 채널 길이에 따른 transient 특성 분석)

  • Kang, Min-Seok;Choi, Chang-Yong;Bang, Wook;Kim, Sang-Chul;Kim, Nam-Kyun;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.131-131
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    • 2009
  • Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

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A New Structure of SOI MOSFETs Using Trench Mrthod (트랜치 기법을 이용한 SOI MOSFET의 전기적인 특성에 관한 연구)

  • Park, Yun-Sik;Sung, Man-Young;Kang, Ey-Goo
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 2003.11a
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    • pp.67-70
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    • 2003
  • In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

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Gate length scaling behavior and improved frequency characteristics of In0.8Ga0.2As high-electron-mobility transistor, a core device for sensor and communication applications (센서 및 통신 응용 핵심 소재 In0.8Ga0.2As HEMT 소자의 게이트 길이 스케일링 및 주파수 특성 개선 연구)

  • Jo, Hyeon-Bhin;Kim, Dae-Hyun
    • Journal of Sensor Science and Technology
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    • v.30 no.6
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    • pp.436-440
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    • 2021
  • The impact of the gate length (Lg) on the DC and high-frequency characteristics of indium-rich In0.8Ga0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (LSD) of 0.8 ㎛ with different values of Lg ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (VT) roll-off behavior against Lg was observed clearly, and the maximum transconductance (gm_max) improved as Lg scaled down to 19 nm. In particular, the device with an Lg of 19 nm with an LSD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a gm_max of 2.5 mS/㎛, On resistance (RON) of 261 Ω·㎛, current-gain cutoff frequency (fT) of 738 GHz, and maximum oscillation frequency (fmax) of 492 GHz. The results indicate that the reduction of Lg to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.