• 대한전자공학회논문지SD
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• 제46권9호
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• pp.14-24
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• 2009

System on panel 프레임 버퍼를 위한 메모리 셀 어레이와 주변회로가 설계되었다. 또한, system on panel 공정의 낮은 yield를 극복하기 위해, 블럭 단위의 parallel test 방안이 제안되었다. 기존의 메모리 테스트 보다 빠르게 fault detection이 가능하며, 다양한 embedded memory나 일반 SRAM 테스트 분야에도 적용 가능하다. 또한 기존의 다양한 test vector pattern이 그대로 적용될 수 있어 fault coverage가 높고, 최근의 추세인 hierarchical bit line과 divided word line 구조에도 적용될 수 있다.

• 대한전기학회논문지:전력기술부문A
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• 제48권5호
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• pp.636-642
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• 1999

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.965-968
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• 2004

This paper describes the development of the test path for Eclipse-II, a parallel mechanism motion simulator. Eclipse-II which can be used as a base for general motion simulators, enables unlimited continuous 360-degree spinning in any rotational axes plus finite X, Y, and Z translation motions. The advantage of enabling continuous 360-degree spinning allows various motions for virtual reality. In this paper, the development of the test path to verify the robustness of the Eclipse-II motion simulator is described. The test motions, which satisfy the requirements of test path, are suggested and washout filter enables these motions reproduced in the limited workspace. The trial run is conducted to verify the robustness of the Eclipse-II motion simulator. Additionally the standard data format of virtual reality for Eclipse-II One Man Ride is suggested.

• 전자공학회논문지C
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• 제35C권8호
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2001년도 춘계 학술대회논문집
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• pp.149-154
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• 2001

Parallel performance of a Myrinet based PC-cluster was tested and compared with a conventional Fast-Ethernet system. A preconditioned Navier-Stokes code was parallelized with domain decomposition technique, and used for the parallel performance test. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network topology. As was expected, Myrinet system shows a superior parallel performance to the Fast-Ethernet system even with a single network adpater for a dual processor SMP machine. A test for the dependency on problem size also shows that network communication speed is a crucial factor for parallelized computational fluid dynamics analysis and the Myrinet system is a plausible candidate for high performance parallel computing system.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권9호
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.157-163
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• 2002

Consideration for parallel operation in a high power system has been increased due to the advantages of parallel operation like as high productivity, simplicity of design, and redundancy of power. This paper discussed the parallel operation of DC-DC Converter, Which Can be used as a high power system, is studied. Based on the small signal model of DC-DC Converter, the simple and exact power stage model of parallel operation system is derived and the parallel operation system using current balance method for the uniform current distribution among the parallel operation system is discussed. To verify the high performance of the proposed DC-DC converter system for parallel operation, the simulation test of the parallel operation, which has 2 Converter modules, is accomplished.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권11호
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• 전자공학회논문지C
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• 제35C권8호
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• pp.10-22
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• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

• 디지털융복합연구
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• 제18권6호
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• pp.271-277
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• 2020

기계번역이란 소스언어를 목적언어로 컴퓨터가 번역하는 소프트웨어를 의미하며 규칙기반, 통계기반 기계번역을 거쳐 최근에는 인공신경망 기반 기계번역에 대한 연구가 활발히 이루어지고 있다. 인공신경망 기계번역에서 중요한 요소 중 하나로 고품질의 병렬 말뭉치를 뽑을 수 있는데 이제까지 한국어 관련 언어쌍의 고품질 병렬 코퍼스를 구하기 쉽지 않은 실정이었다. 최근 한국정보화진흥원의 AI HUB에서 고품질의 160만 문장의 한-영 기계번역 병렬 말뭉치를 공개하였다. 이에 본 논문은 AI HUB에서 공개한 데이터 및 현재까지 가장 많이 쓰인 한-영 병렬 데이터인 OpenSubtitles와 성능 비교를 통해 각각의 데이터의 품질을 검증하고자 한다. 테스트 데이터로 한-영 기계번역 관련 공식 테스트셋인 IWSLT에서 공개한 테스트셋을 이용하여 보다 객관성을 확보하였다. 실험결과 동일한 테스트셋으로 실험한 기존의 한-영 기계번역 관련 논문들보다 좋은 성능을 보임을 알 수 있었으며 이를 통해 고품질 데이터의 중요성을 알 수 있었다.