• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.5
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• pp.636-642
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• 1999

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.965-968
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• 2004

This paper describes the development of the test path for Eclipse-II, a parallel mechanism motion simulator. Eclipse-II which can be used as a base for general motion simulators, enables unlimited continuous 360-degree spinning in any rotational axes plus finite X, Y, and Z translation motions. The advantage of enabling continuous 360-degree spinning allows various motions for virtual reality. In this paper, the development of the test path to verify the robustness of the Eclipse-II motion simulator is described. The test motions, which satisfy the requirements of test path, are suggested and washout filter enables these motions reproduced in the limited workspace. The trial run is conducted to verify the robustness of the Eclipse-II motion simulator. Additionally the standard data format of virtual reality for Eclipse-II One Man Ride is suggested.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.1-9
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• 1998

A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

• 한국전산유체공학회:학술대회논문집
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• 2001.05a
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• pp.149-154
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• 2001

Parallel performance of a Myrinet based PC-cluster was tested and compared with a conventional Fast-Ethernet system. A preconditioned Navier-Stokes code was parallelized with domain decomposition technique, and used for the parallel performance test. Speed-up ratio was examined as a major performance parameter depending on the number of processor and the network topology. As was expected, Myrinet system shows a superior parallel performance to the Fast-Ethernet system even with a single network adpater for a dual processor SMP machine. A test for the dependency on problem size also shows that network communication speed is a crucial factor for parallelized computational fluid dynamics analysis and the Myrinet system is a plausible candidate for high performance parallel computing system.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.9
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2002.11a
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• pp.157-163
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• 2002

Consideration for parallel operation in a high power system has been increased due to the advantages of parallel operation like as high productivity, simplicity of design, and redundancy of power. This paper discussed the parallel operation of DC-DC Converter, Which Can be used as a high power system, is studied. Based on the small signal model of DC-DC Converter, the simple and exact power stage model of parallel operation system is derived and the parallel operation system using current balance method for the uniform current distribution among the parallel operation system is discussed. To verify the high performance of the proposed DC-DC converter system for parallel operation, the simulation test of the parallel operation, which has 2 Converter modules, is accomplished.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.11
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.10-22
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• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

• Journal of Digital Convergence
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• v.18 no.6
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• pp.271-277
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• 2020

Machine translation refers to software that translates a source language into a target language, and has been actively researching Neural Machine Translation through rule-based and statistical-based machine translation. One of the important factors in the Neural Machine Translation is to extract high quality parallel corpus, which has not been easy to find high quality parallel corpus of Korean language pairs. Recently, the AI HUB of the National Information Society Agency(NIA) unveiled a high-quality 1.6 million sentences Korean-English parallel corpus. This paper attempts to verify the quality of each data through performance comparison with the data published by AI Hub and OpenSubtitles, the most popular Korean-English parallel corpus. As test data, objectivity was secured by using test set published by IWSLT, official test set for Korean-English machine translation. Experimental results show better performance than the existing papers tested with the same test set, and this shows the importance of high quality data.