• Journal of Mechanical Science and Technology
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• 제20권1호
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• pp.125-132
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• 2006

To understand fluid dynamic forces acting on a structure subjected to two-phase flow, it is essential to get detailed information about the characteristics of two-phase flow. Stratified steady and unsteady two-phase flows between two parallel plates have been studied to investigate the general characteristics of the flow related to flow-induced vibration. Based on the spectral collocation method, a numerical approach has been developed for the unsteady two-phase flow. The method is validated by comparing numerical result to analytical one given for a simple harmonic two-phase flow. The flow parameters for the steady two-phase flow, such as void fraction and two-phase frictional multiplier, are evaluated. The dynamic characteristics of the unsteady two-phase flow, including the void fraction effect on the complex unsteady pressure, are illustrated.

• Journal of Advanced Marine Engineering and Technology
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• 제24권3호
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• pp.106-112
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• 2000

Since the oil crisis, we have been concerned about the energy saving techniques of electric generating systems. As a part of the effort to save energy, automatic electric load sharing device was developed. Usually, ship's electric generating system consists of two or three sets of generator. And, electric generating system is operated as single or parallel operation mode according to the demanded electric power. Therefore, it is important to investigate generators operating mode for the supply of required electric power in the ship in order to decrease the operating cost. So, this paper suggests the method to solve the optimal electric load distribution problem by dynamic programming. And, this thesis indicates that the proposed method is superior to the lagrange multiplier's method in obtaining optimal load distribution solution in the ship's electric generating system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.773-776
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• 2003

This paper presents new hardware implementation of the ECC(Elliptic Curve Cryptography) algorithm that is improved in speed and stability. We proposed new datapath that changed square's position so that we can reduce required number of cycles for addition operation between two points by more than 30%. We used Massey-Omura parallel multiplier adopted Normal basis for fast scalar multiplications. Also the use of the window non-adjacent form (WNAF) method can reduce addition operation of each other different points. We implemented ECC system with GF($2^{196}$), and this system was designed and verified by VHDL.

• 대한임베디드공학회논문지
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• 제14권6호
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• pp.313-319
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• 2019

Finite field operations have played an important role in error correcting codes and cryptosystems. Recently, the necessity of efficient computation processing is increasing for security in cyber physics systems. Therefore, efficient implementation of finite field arithmetics is more urgently needed. These operations include addition, multiplication, division and inversion. Addition is very simple and can be implemented with XOR operation. The others are somewhat more complicated than addition. Among these operations, multiplication is the most important, since time-consuming operations, such as exponentiation, division, and computing multiplicative inverse, can be performed through iterative multiplications. In this paper, we propose a multiplexer based parallel computation algorithm that performs Montgomery multiplication over finite field using redundant basis. Then we propose an efficient multiplexer based semi-systolic multiplier over finite field using redundant basis. The proposed multiplier has less area-time (AT) complexity than related multipliers. In detail, the AT complexity of the proposed multiplier is improved by approximately 19% and 65% compared to the multipliers of Kim-Han and Choi-Lee, respectively. Therefore, our multiplier is suitable for VLSI implementation and can be easily applied as the basic building block for various applications.

• 전자공학회논문지B
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• 제33B권1호
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• pp.25-37
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• 1996

실시간 컴퓨터 그래픽 처리를 위하여는 고속 연산(승산 및 가산)회로가 필요하다. 잉여수 체계(RNS:Residue Number System)는 병렬성과 고속성을 갖는 정수연산체계이고, 또한 순환군(cyclic group)은 가산과 승산이 동형인 잉여수 연산을 수행하므로 고속의 승산기와 가산기의 설계가 가능하다. 그러므로, 본 논문에서는 DRNS(Double Residue Number System)를 제안하고, 순환부호(circula- tive code)를 이용한 고속의 잉여수 승산기를 설계하여, 이를 그래픽 프로세서의 연산기로 사용하고자 한다. 설계된 승산기는 TTL소자 74s09, 74s32를 사용한 경우 87MHz속도의 연산이 가능하다.

• 정보보호학회논문지
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• 제17권4호
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• pp.97-102
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• 2007

본 논문에서는 $GF(2^m)$ 상의 새로운 저복잡도 고속-직렬 곱셈기 구조를 제안하였다. 고속-직렬 곱셈기는 유한체 $GF(2^m)$의 표준기저 상에서 동작하며, 직렬 곱셈기 보다는 짧은 지연시간에 결과를 얻을 수 있고, 병렬 곱셈기 보다는 적은 하드웨어로 구현할 수 있다. 이 고속-직렬 곱셈기는 회로의 복잡도와 지연시간 사이에 적절한 절충을 꾀할 수 있는 장점을 가지고 있다. 그러나 기존의 고속-직렬 곱셈기는 t배의 속도를 향상시키기 위하여 (t-1)m개의 레지스터가 더 사용되었다. 본 논문에서는 레지스터 수를 증가시키지 않는 새로운 고속-직렬 곱셈기를 설계하였다.

• 한국정보보호학회:학술대회논문집
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• 한국정보보호학회 1996년도 종합학술발표회논문집
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• pp.165-174
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• 1996

• 대한전기학회:학술대회논문집
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• 대한전기학회 1985년도 하계학술회의논문집
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• pp.246-248
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• 1985

• 전자공학회논문지C
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• 제35C권2호
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• 한국컴퓨터정보학회논문지
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• 제17권3호
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• pp.1-10
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• 2012

본 논문에서는 계수순환과 기약 삼항식을 적용하여 시스템 복잡도를 개선한 GF($2^m$)상의 승산기 구성방법과 구현회로를 제안하였다. 제안된 회로는 병렬 입출력 구조를 가지며, 승산항의 계수 순환과 기약 삼항식을 적용한 모듈로 연산을 하는 회로 구성의 특성상 기존의 타 논문에 비해 회로 복잡도가 감소함을 보였다. 본 논문에서 제안한 회로의 시스템 복잡도는 $2m^2$개의 2-입력 AND 게이트, m (m+2)개의 2-입력 XOR 게이트의 회로복잡도이며, 메모리나 스위치 등의 별도의 소자는 필요하지 않다. 연산에 소요되는 최대 지연시간은 $T_A+(2+{\lceil}log_2m{\rceil})T_X$ 이다. 본 논문에서 제안한 회로는 간단하고, 정규성을 보이며, 모듈구성이 가능하기 때문에 VLSI 회로구성에 상대적으로 적합하다.