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http://dx.doi.org/10.13089/JKIISC.2007.17.4.97

Low Complexity Architecture for Fast-Serial Multiplier in $GF(2^m)$  

Cho, Yong-Suk (Youngdong University)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.17, no.4, 2007 , pp. 97-102 More about this Journal
Abstract
In this paper, a new architecture for fast-serial $GF(2^m)$ multiplier with low hardware complexity is proposed. The fast-serial multiplier operates standard basis of $GF(2^m)$ and is faster than bit serial ones but with lower area complexity than bit parallel ones. The most significant feature of the fast-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But The traditional fast-serial architecture needs extra (t-1)m registers for achieving the t times speed. In this paper a new fast-serial multiplier without increasing the number of registers is presented.
Keywords
Finite fields; Multiplier; Error-control coding; Cryptography;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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