• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.11
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• pp.1646-1655
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• 2004

A description of the basic principles of moire interferometry leads to the design of a eight-mirror four-beam interferometer for obtaining fringe patterns representing contour-maps of in-Plane displacements. The technique is implemented by the optical system using an environmental chamber for submicro-displacement mesurement. In order to estimate the reliability and applicabili쇼 of the system developed, the measurement of coefficient of thermal expansion (CTE) for a aluminium block is performed. Consequently, the system is applied to the measurement of thermal deformation of a WB-PBGA package assembly. Temperature dependent analyses of global and local deformations are presented to study the effect of the mismatch of CTE between materials composed of the package assemblies. Bending displacements of the packages and average strains of solder balls are documented. Thermal induced displacements calculated by FEM agree quantitatively with experimental results.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.55-65
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• 2020

The use of underfill materials in semiconductor packages is not only important for stress relieving of the package, but also for improving the reliability of the package during shock and vibration. However, in recent years, as the size of the package becomes larger and very thin, the use of the underfill shows adverse effects and rather deteriorates the reliability of the package. To resolve these issues, we developed the package using a solid epoxy material to improve the reliability of the package as a substitute for underfill material. The developed solid epoxy was applied to the package of the application processor in smart phone, and the reliability of the package was evaluated using thermal cycling reliability tests and numerical analysis. In order to find the optimal solid epoxy material and process conditions for improving the reliability, the effects of various factors on the reliability, such as the application number of solid epoxy, type of PCB pad, and different solid epoxy materials, were investigated. The reliability test results indicated that the package with solid epoxy exhibited higher reliability than that without solid epoxy. The application of solid epoxy at six locations showed higher reliability than that of solid epoxy at four locations indicating that the solid epoxy plays a role in relieving stress of the package, thereby improving the reliability of the package. For the different types of PCB pad, NSMD (non-solder mask defined) pad showed higher reliability than the SMD (solder mask defined) pad. This is because the application of the NSMD pad is more advantageous in terms of thermomechanical stress reliability because the solderpad bond area is larger. In addition, for the different solid epoxy materials with different thermal expansion coefficients, the reliability was more improved when solid epoxy having lower thermal expansion coefficient was used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.8-13
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• 2006

Recent RF SAW filters are made using a HTCC package with a CSP(chip scale Package) technology. This paper describes a development of a new $1.4{\times}1.1\;and\;2.0{\times}1.4mm$ RF SAW liters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.7-17
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• 2014

Power electronics modules are semiconductor components that are widely used in airplanes, trains, automobiles, and energy generation and conversion facilities. In particular, insulated gate bipolar transistors(IGBT) have been widely utilized in high power and fast switching applications for power management including power supplies, uninterruptible power systems, and AC/DC converters. In these days, IGBT are the predominant power semiconductors for high current applications in electrical and hybrid vehicles application. In these application environments, the physical conditions are often severe with strong electric currents, high voltage, high temperature, high humidity, and vibrations. Therefore, IGBT module packages involves a number of challenges for the design engineer in terms of reliability. Thermal and thermal-mechanical management are critical for power electronics modules. The failure mechanisms that limit the number of power cycles are caused by the coefficient of thermal expansion mismatch between the materials used in the IGBT modules. All interfaces in the module could be locations for potential failures. Therefore, a proper thermal design where the temperature does not exceed an allowable limit of the devices has been a key factor in developing IGBT modules. In this paper, we discussed the effects of various package materials on heat dissipation and thermal management, as well as recent technology of the new package materials.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.3.2-3.2
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• 2009

Development of printed electronics, which is occasionally referred to as 'flexible' or 'polymer' electronics, has attracted considerable world wide attention in recent years. Printed (or flexible) electronics is currently expected to represent a new form of electronics and open up wide ranging applications in displays, electron devices for medical use, sensors, and other areas. This presentation aims to provide a strategy for scalable and viable paths to accomplish flexible, printable, large area circuits displaying high performance. Novel approaches evolving from system on package (SoP) to system on flex (SoF) technology will allow the integration of heterogeneous materials platforms into a system which is needed to enhance the functionality of the system. The talk also includes speculations about areas on which future advances in printed electronics could have a substantial impact along with a brief introduction of the Korea Printed Electronics Association (KoPEA).

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.407-411
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• 2000

Low-temperature solder glass for use in electronic package was experimentally prepared and its crystallization behavior was investigated using differential thermal analysis (DTA) under nonisothermal condition. The composition of the solder glass was determined from PbO-ZnO-$B_2$$O_3$-$TiO_2$ glasses containing small amounts of CaO, $SiO_2$$A1_2$$O_3$ and $P_2$$O_5$. The crystallization exotherm corresponding to the formation of lead titanate (PbTiO$_3$) was observed. The crystallization of $PbTiO_3$was a three-dimensional process with the average activation energy of 223$\pm$3 kJ/mol for the crystallization from the glass matrix.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.4
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• pp.1-10
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• 2015

The light emitting diodes(LED) package of new structure is proposed to promote the reliability and lifespan by maximize heat dissipation occurred on the chip. We designed and fabricated the LED packages mixing the advantages of chip on board(COB) based on conventional metal printed circuit board(PCB) and the merits of Si sub-mount using base as a substrate. The proposed LED package samples were selected for the superior efficiency of the material through the sealant properties, chip characteristics, and phosphor properties evaluations. Reliability test was conducted the thermal shock test and flux rate according to the usage time at room temperature, high-temperature operation, high-temperature operation, high-temperature storage, low-temperature storage, high-temperature and high-humidity storage. Reliability test result, the average flux rate was maintained at 97.04% for each items. Thus, the Si sub-mount based LED package is expected to be applicable to high power down-light type LED light sources.