• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• Journal of the Korean Society for Heat Treatment
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• v.28 no.1
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• pp.7-16
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• 2015

The fabrication of high quality graphene using chemical vapor deposition (CVD) method for application in semiconductor, display and transparent electrodes is investigated. Temperature and pressure have major impact on the growth of graphene. Graphene doping was obtained by deposition of $MoO_3$ thin films using thermal evaporator. Bilayer graphene and the metal layer graphene were obtained. According to the behavior of graphene growth P-type doping was confirmed. Graphene obtained through experiments was analyzed using optical microscopy, Raman spectroscopy, UV-visible light spectrophotometer, 4-point probe sheet resistance meter and atomic force microscopy.

• 전기의세계
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• v.26 no.5
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• pp.83-89
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• 1977

This paper described the minority carrier lifetime in Si epitaxial layer, and also the voltage (V) versus current (I) characteristics of high resistivity Si epitaxial layer0substrate junction. The measured lifetime in Si epi-layer was much shorter than in bulk, and the temperature dependence of lifetime was found to agree well with Shockley-Read model of recombination which applies to high resistivity n-type materials. The V-I curve showed; an ohmic region (I.var.V), a sublinear region (I.var.V$^{1}$2/), a space charge limited current region (I.var.V$^{2}$), and finally a negative resistance region. We investigated these phenomena by the theory of the relaxation semiconductor.

• Journal of Sensor Science and Technology
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• v.16 no.1
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• pp.11-16
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• 2007

CuO is an important transition metal oxide with many practical applications such as catalysts, p-type semiconductor, solar cells, magnetic storage media and cathode materials. In this contribution, nanocrystalline CuO powders were prepared by solution reduction method using copper chloride ($CuCl_{2}{\cdot}2H_{2}O$), hydrazine ($N_{2}H_{4}$) and NaOH and subsequent heat treatment. The gas sensor using nanocrystalline CuO powders showed high sensitivities to acetone and ethanol.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.666-666
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• 2013

CIGS solar cell에서 p-type semiconductor역할을 수행하는 Cu(In,Ga)Se로 이루어진 Absorber layer는 4 element multi binary compound로 stoichiometry 측면에서 다양한 형태가 나타나기 때문에 태양전지 효율을 향상시키기 위해 이에 대한 연구가 활발하다. 우리는 E-beam evaporation 방법으로 다양한 조건의 multi layer로 증착된 CIG layer 위에 일정 두께의 Se을 증착하면서 열처리 조건에 따른 Selenization 메커니즘에 대한 연구를 수행하였다. 결과분석을 위해(in-situ High Temperature) XRD, XPS, Micro Raman spectroscopy, FE-SEM, (Nano Indentor, Atomic Force Microscopy) 등을 이용하여 결정구조, 결정화도, Depth profile, Eg (band gap energy) 등을 알아보고 분석결과간의 상관관계를 고찰하였다.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.878-882
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• 2004

Position controls are very important in semiconductor manufacturing devices, machine tools precision measuring instruments, etc. In this paper, a novel encoder of digital and analog hybrid type is proposed. It is shown that from this experiment a high-resolution angle measurement device can be designed by a low cost incremental encoder.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.828-831
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• 2001

A simple and versatile method of manufacturing semiconductor devices with pn-junctions used the silicon direct bonding technology with simultaneous impurity diffusion is suggested . Formation of p- or n- type layers was tried during the bonding procedure by attaching two wafers in the aqueous solutions of Al(NO$_3$)$_3$, Ga(NO$_3$)$_3$, HBO$_3$, or H$_3$PO$_4$. An essential improvement of bonding interface structural quality was detected and a model for the explanation is suggested. Diode, Dynistor, and BGGTO structures were fabricated and examined. Their switching characteristics are presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.93-94
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• 2006

나노급 CMOS 기술에서 high-k 물질을 이용하여 게이트 유전막을 형성하고자 하는 연구가 활발히 진행되고 있다. 본 논문에서는 high-k 물질인 $TiO_2$의 특성에 대한 연구를 수행하였다. $TiO_2$를 APCVD법으로 p-type 실리콘 기판에 $50{\AA}{\sim}300{\AA}$ 두께로 증착하였고, evaporator를 이용하여 $TiO_2$ 박막위에 Al을 증착하여 MIS소자를 제작하였다. 두께를 가변 하여 Capacitance-Voltage (C-V) 특성을 측정, 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.695-701
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• 2016

Be-doped GaSb layers were grown on highly mismatched semi-insulating GaAs substrate (001) with $2^{\circ}$ offcut towards <110> at low growth temperature, by molecular beam epitaxy (MBE). The influence of Be doping on the crystallographic quality, surface morphology, and electrical properties, was assessed by X-ray diffraction, Nomarski microscopy, and Hall effect measurements, respectively. Be impurities are well behaved acceptors with hole concentrations as high as $9{\times}10^{17}cm^{-3}$. In addition, the reduction of GaSb lattice parameter with Be doping was studied.

• ETRI Journal
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• v.20 no.1
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• pp.37-45
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• 1998

Reduced surface field lateral double-diffused MOS transistor for the driving circuits of plasma display panel and field emission display in the 120V region have been integrated for the first time into a low-voltage $1.2{\mu}m$ analog CMOS process using p-type bulk silicon. This method of integration provides an excellent way of achieving both high power and low voltage functions on the same chip; it reduces the number of mask layers double-diffused MOS transistor with a drift length of $6.0{\mu}m$ and a breakdown voltage greater than 150V was self-isolated to the low voltage CMOS ICs. The measured specific on-resistance of the lateral double-diffused MOS in $4.8m{\Omega}{\cdot}cm^2$ at a gate voltage of 5V.