• Applied Science and Convergence Technology
• /
• 제25권6호
• /
• pp.124-127
• /
• 2016

Humidity calibration for a temperature-stable quartz oscillator (TSQO) was investigated to exclude the influences of relative humidity on the TSQO output in order to use the corresponding devices outdoors. The TSQO output is a voltage that is inversely proportional to the electric impedance of the quartz oscillator, which depends on the viscosity and density of the measured gas. The TSQO output was humidity calibrated using its humidity dependence, which was obtained by varying the relative humidity (RH) from 0 to 100 RH% while other conditions were kept constant. The humidity dependencies of the TSQO output were fit by a linear function. Subtracting the change in the TSQO output induced by the change in humidity, calculated with the function from the experimentally measured TSQO output for a range of 0-100RH%, eliminated the influence of humidity on the TSQO output. The humidity calibration succeeded in reducing the fluctuations of the TSQO output from 0.4-3% to 0.1-0.3% of the average values for a range of 0-100RH%, at constant temperatures. The necessary stability of the TSQO output for application in hydrogen sensors was below one-third of the change observed for a hydrogen leakage of 1 vol.% hydrogen concentration, corresponding to 0.33% of the change in each background. Therefore, the results in this study indicate that the present humidity calibration effectively suppresses the influence of humidity, for the TSQO output for use as an outdoor hydrogen sensor.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제13권5호
• /
• pp.423-429
• /
• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제9권1호
• /
• pp.14-21
• /
• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• 한국정보통신학회논문지
• /
• 제20권1호
• /
• pp.110-116
• /
• 2016

본 논문에서는 디지털 임피던스 보정 회로와 이퀄라이저 회로를 가진 1.2V 5Gb/s SLVS 차동 송신단을 제안한다. 제안하는 송신단은 4-위상 출력 클록을 갖는 위상 고정 루프, 4-to-1 직렬변환기, 레귤레이터, 출력 드라이버, 그리고 신호보존성을 향상하기 위한 이퀄라이저 회로를 포함한다. 또한, built-in self-test를 위해 pseudo random bit sequence 발생기를 함께 구현한다. 제안하는 SLVS 송신단은 80mV에서 500mV의 차동 출력 전압범위를 지원한다. SLVS 송신단은 1.2V의 공급전압을 가지는 65nm CMOS공정을 이용하여 구현한다. 측정된 5Gb/s SLVS 송신단의 peak-to-peak 시간 지터는 46.67ps이며, 전력소모는 1.88mW/Gb/s이다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권1호
• /
• pp.126-142
• /
• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

• 한국산업정보학회논문지
• /
• 제18권5호
• /
• pp.25-32
• /
• 2013

고속 저전력 모바일 응용분야를 위한 1.8V 2-Gb/s scalable low voltage signaling (SLVS) 송신단을 제안한다. 제안하는 송신단은 데이터 전송을 위한 4-lane 송신단, 소스 동기 클록 방식을 위한 1-lane 송신단, 그리고 8-phase 클록 발생기로 구성된다. 제안하는 SLVS 송신단은 50 mV에서 650 mV의 출력 전압 범위를 가지며 고속 동작 모드와 저전력 모드를 제공한다. 또한, signal integrity를 개선하기 위한 출력 드라이버의 임피던스 교정 기법이 제안된다. 제안하는 SLVS 송신단은 1.8 V의 공급 전압을 가지는 0.18-${\mu}m$ 1-poly 6-metal CMOS 공정을 이용하여 구현된다. 구현된 SLVS 송신단의 데이터 jitter의 시뮬레이션 결과는 2-Gb/s의 데이터 전송속도에서 8.04 ps이다. 1-lane을 위한 SLVS 송신단의 면적과 전력소모는 각각 $422{\times}474{\mu}m^2$와 5.35 mW/Gb/s이다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권3호
• /
• pp.270-277
• /
• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• 대한기계학회논문집B
• /
• 제27권6호
• /
• pp.714-725
• /
• 2003

The theory of the current-type electromagnetic flowmeter for a high temporal resolution was developed for two-phase flow measurements. To predict the output of the current-type flowmeter, the three-dimensional virtual potential distribution C and the newly introduced flow pattern coefficient f were derived and computed. The output of flowmeter depends on the liquid conductivity (sensitive to temperature) and flow configurations of the two-phase flow with the sinusoidal excitation over 100 Hz. The flow pattern coefficient was specially devised to separate the dependency on the flow configuration of the two-phase flow from that on the liquid conductivity which can be expressed with the calibration of single-phase flow. Using the finite difference method, the three-dimensional virtual potential distributions were computed for the electrode of finite size. By taking derivative of the virtual potential, the weight functions were evaluated and compared with existing analytic series solution for the point-electrode. There was a reasonable correspondence between the present and existing results. In addition, the flow pattern coefficients were evaluated for annular flows with various film thicknesses, and compared with the experimental results by the impedance spectroscopy. The numerical results agreed well with the experimental data.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.523-523
• /
• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2013년도 추계학술대회
• /
• pp.357-360
• /
• 2013

고속 저전력 모바일 응용분야를 위한 1.8V 2-Gb/s SLVS 송신단을 제안한다. 제안하는 송신단은 데이터 전송을 위한 4-lane 송신단, 소스 동기 클럭 방식을 위한 1-lane 송신단, 그리고 8-phase 클럭 발생기로 구성된다. 제안하는 SLVS 송신단은 50 mV에서 650 mV의 출력 전압 범위를 가지며 고속 동작 모드와 저전력 모드를 제공한다. 또한, signal integrity를 개선하기 위한 출력 드라이버의 임피던스 교정 기법이 제안된다. 제안하는 SLVS 송신단은 1.8V의 공급 전압을 가지는 $0.18-{\mu}m$ 1-poly 6-metal CMOS 공정을 이용하여 구현된다. 구현된 SLVS 송신단의 데이터 jitter의 시뮬레이션 결과는 2-Gb/s의 데이터 전송속도에서 8.04 ps이다. 1-lane을 위한 SLVS 송신단의 면적과 전력소모는 각각 $422{\times}474{\mu}m^2$와 5.35 mW/Gb/s이다.