• Journal of the Korean Society for Precision Engineering
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• v.17 no.12
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• pp.176-184
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• 2000

TDC(Time Delay Control) deals with the time-varying system parameters, unknown dynamics and unexpected disturbances using time delay. TDC can be divided into two separate parts: an auxiliary controller and a servo controller. The two controllers can be designed independently. The auxiliary controller is used to reduce sensitivity to parameter variations, nonlinear effects, and other disturbances. The servo controller is to reduce the error between the desired command and output. We propose the model-following time delay controller with modified error feedback controller. This was applied to follow the desired reference model for the uncertain time-varying overhead crane. The model generates the damped-out swinging motion trajectory to suppress the swinging motion caused by the acceleration and the deceleration of crane transportation. The control performance was evaluated through simulations. The theoretical results indicate that this control method shows excellent performance to an overhead crane with the uncertain time-varying parameters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.479-491
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• 1994

In this paper, we proposed cell priority control with 2-level thresholds, which was considered cell loss and cell delay requirement, in ATM switch with output buffer. Priority control mechanism presented in this paper improved cell loss rate for cell loss censitive cell and cell delay for delay censitive cell. In this mechanism cell loss rate and mean cell delay of cell priority control mechanism were obtained theoretically. The results show that cell loss rate and mean cell delay improvement become better by adjusting two thresholds according to QOS characteristics.

• The Journal of the Acoustical Society of Korea
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• v.40 no.5
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• pp.452-459
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• 2021

Estimating the mutual time delay between two acoustic sensors is used in various fields such as tracking and estimating the location of a target in room acoustics and sonar. In the time delay estimation methods, there are a non-parametric method, such as Generalized Cross Correlation (GCC), and a parametric method based on system identification. In this paper, we propose a time delay estimation method based on the parametric method. In particular, we propose a method that considers the noise in each receiving acoustic sensor. Simulation confirms that the proposed algorithm is superior to the existing generalized cross-correlation and adaptive eigenvalue analysis methods in white noise and reverberation environments.

• Journal of IKEEE
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• v.23 no.3
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) circuit is a basic component of 4-2 compressor for high performance arithmetic operation. In this paper we propose an energy efficient XOR-XNOR circuit. The proposed circuit is reduced the internal parasitic capacitance in critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit has a 14.5% reduction in propagation delay time and a 1.7% increase in power consumption. Therefore, the proposed XOR-XNOR is reduced power-delay- product (PDP) by 13.1% and energy-delay-product (EDP) by 26.0%. The proposed circuits are implemented with standard CMOS 0.18um technology and verified through SPICE simulation with 1.8V supply voltage.

• Journal of IKEEE
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• v.28 no.1
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• pp.1-5
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• 2024

To improve the performance of DRAM, it is essential to reduce sensing failures caused by mismatch in SA. Unlike flip failures, delay failures can be degraded, especially when high-speed operation is required, making it a critical consideration in the design of next-generation memory. While conventional SA operates with all transistors starting amplification simultaneously, SDSA selectively activates only two transistors that output BLB, thus alleviating offset. In this paper, we validate the superior performance of SDSA in mitigating delay failures through simulations. It was confirmed that SDSA exhibits approximately a 90 % reduction in delay failures compared to conventional SA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.924-927
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• 2017

This paper presents a 6~18 GHz 8-bit true time delay (TTD) circuit. The unit delay circuit is based on m-derived filter with relatively constant group delay. The designed 8-bit TTD is implemented with two single-pole double-throw (SPDT) switches and seven double- pole double-throw (DPDT) switches. The reflection characteristics are improved by using inductors. The designed 8-bit TTD was fabricated using $0.18{\mu}m$ CMOS. The measured delay control range was 250 ps with 1 ps of delay resolution. The measured RMS group delay error was less than 11 ps at 6~18 GHz. The measured input/output return losses are better than 10 dB. The chip consumes zero power at 1.8 V supply. The chip size is $2.36{\times}1.04mm^2$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.2
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• pp.69-76
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• 2023

A high-quality audio/voice codec using the MDCT/IMDCT process can perfectly restore the current frame through an overlap-add process with the previous frame. In the overlap-add process, an algorithm delay equal to the frame length occurs. In this paper, we propose a MDCT/IMDCT process that reduces algorithm delay by using a variable phase shift in MDCT/IMDCT process. In this paper, a low-delay audio/speech codec was proposed by applying the low delay MDCT/IMDCT algorithm to the ITU-T standard codec G.729.1 codec. The algorithm delay in the MDCT/IMDCT process can be reduced from 20 ms to 1.25 ms. The performance of the decoded output signal of the audio/speech codec to which low-delay MDCT/IMDCT is applied is evaluated through the PESQ test, which is an objective quality test method. Despite of the reduction in transmission delay, it was confirmed that there is no difference in sound quality from the conventional method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.7
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• pp.113-121
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• 2005

In this paper, a constant output power supply system for ozonizer is proposed to remove the noise of ozonizer and control the output of ozonizer using feedback control. The proposed system is based on the rouble control loop such as the outer voltage control loop and inner current control loop. In the proposed system overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the experimental results.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.1
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• pp.58-66
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• 1991

In inverters, time delays are inserted in the switching signals to prevent the dc lind shortage. This causes detrimental effects on the performance of the inverters, that is, the fundamental voltage drop and the generation of low order harmonics. This paper derives simple formula to describe the time delay effects in PWM inverters, where the effects may become significant because of relatively high switching frequencies. To compensate the tice delay effects, this paper presents two methods which are suitable for sinusoidal PWM and memory-based PWM respectively. Both are simple, easy to implement, and are shown to be effective, through the experiments, in improving the output waveform of PWM inverters.