Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Analysis of Improvement on Delay Failures in Separated Driving-line Sense Amplifier

구동라인분리 센스앰프의 딜레이페일 개선 효과에 대한 분석

  • Dong-Yeong Kim (Department of ICT Convergence System Engineering, Chonnam National University) ;
  • Su-Yeon Kim (Department of ICT Convergence System Engineering, Chonnam National University) ;
  • Je-Won Park (Department of ICT Convergence System Engineering, Chonnam National University) ;
  • Sin-Wook Kim (Department of ICT Convergence System Engineering, Chonnam National University) ;
  • Myoung Jin Lee (Department of ICT Convergence System Engineering, Chonnam National University)
  • Received : 2024.02.21
  • Accepted : 2024.02.28
  • Published : 2024.03.31
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Abstract

To improve the performance of DRAM, it is essential to reduce sensing failures caused by mismatch in SA. Unlike flip failures, delay failures can be degraded, especially when high-speed operation is required, making it a critical consideration in the design of next-generation memory. While conventional SA operates with all transistors starting amplification simultaneously, SDSA selectively activates only two transistors that output BLB, thus alleviating offset. In this paper, we validate the superior performance of SDSA in mitigating delay failures through simulations. It was confirmed that SDSA exhibits approximately a 90 % reduction in delay failures compared to conventional SA.

DRAM의 성능 개선을 위해 센스앰프의 미스매치로 인한 센싱페일을 감소시켜야 한다. 플립페일과 달리 딜레이페일은 고속 동작이 요구될 때 더 심화될 수 있어 차세대 메모리 설계 시 면밀히 고려되어야 할 문제이다. Conventional SA는 증폭 시작 시 모든 트랜지스터가 동시에 동작하는 반면, SDSA는 BLB를 출력으로 하는 트랜지스터 2개만 먼저 동작시켜 오프셋을 완화할 수 있다. 본 논문에서는 SDSA의 딜레이페일에 대한 우수성을 시뮬레이션을 통해 검증하였다. Conventional SA에 비해 약 90%의 딜레이 페일 감소 효과를 갖고 있음을 확인했다.

Keywords

Acknowledgement

This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the ICAN(ICT Challenge and Advanced Network of HRD) program(IITP-2023-RS-2022-00156385) supervised by the IITP(Institute of Information & Communications Technology Planning & Evaluation). This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the Innovative Human Resource Development for Local Intellectualization support program(IITP-2023-RS-2022-00156287) supervised by the IITP(Institute for Information & communications Technology Planning & Evaluation). This research was supported by the BK21 FOUR Program(Fostering Outstanding Universities for Research, 5199991714138) funded by the Ministry of Education(MOE, Korea) and National Research Foundation of Korea(NRF). The EDA tool was supported by the IC Design Education Center (IDEC), South Korea.

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