• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3184-3186
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• 1999

In this paper, a new structure of fully differential delay cell VCO using quadrature phase for low phase noise and high speed operation is suggested. It is realized by inserting voltage clamp circuit into input pairs of delay cells that include three-control current source having high output impedance. In this reason. this newly designed delay cell for VCO has the low power supply sensitivity so that the phase noise can be reduced. The whole characteristics of VCO were simulated by using HSPICE and SABER. Simulation results show that the phase noise of new VCO is quite small compared with conventional fully differential delay cell VCO and ring oscillator type VCO. It is also very beneficial to low power supply design because of wide tuning range.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.123-126
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• 2003

RSFQ (Rapid Single Flux Quantum) circuits are used in many practical applications. RSFQ DFFC (Delay Flip-Flop with complementary outputs) circuits can be used in a RAM, an ALU (Arithmetic Logic Unit), a microprocessor, and many communication devices. A DFFC circuit has one input, one switch input, and two outputs (output l and output 2). DFFC circuit functions in such way that output 1 follows the input and output 2 is the complement of the input when the switch input is "0." However, when there is a switch input "1."the opposite output signals are generated. In this work, we have designed an RSFQ DFFC circuit based on 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology. As circuit design tools, we used Xic, WRspice, and Lmeter After circuit optimization, we could obtain the bias current margins of the DFFC circuit to be above 32％.

• Journal of Power Electronics
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• v.15 no.4
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• pp.886-898
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• 2015

The design feasibility of a micro unidirectional DC transmission system based on an input-parallel output-parallel (IPOP) converter is analyzed in this paper. The system consists of two subsystems: an input-parallel output-series (IPOS) subsystem to step up the DC link voltage, and an input-series output-parallel (ISOP) subsystem to step down the output voltage. The two systems are connected through a transmission line. The challenge of the delay caused by the communication in the control system is addressed by introducing a ring communication structure, and its influence on the control system is analyzed to ensure the feasibility and required performance of the converter system under practical circumstances. Simulation and experiment results are presented to verify the effectiveness of the proposed design.

• Proceedings of the KIEE Conference
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• 2004.05a
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• pp.47-49
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• 2004

In this correspondence, an new approach to design a fuzzy controller for system with uncertain output backlash to have good tracking performance is presented. Without using a compensation mechanism or backlash inverse, the fuzzy control mechanism is designed to implicitly compensate the delay effect arising from an uncertain output backlash and to make the output backlash stable without limit cycles. The proposed method designs a model-based fuzzy controller for a one-input one-output linear plant with output backlash. The effectiveness of the designed fuzzy controller is illustrated by the simulation.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.68-69
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• 2011

Realistic amounts of time delay are found to have significant effects on the average output LED current and on the critical inductor value at the boundary between the two conduction modes. Especially, the time delay can provide an accurate LED current for the peak current controlled (PCC) buck converter with a wide input voltage. Experimental results are presented for the PCC buck LED driver with constant-frequency controller.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.299-303
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• 1995

This paper charcterizes dynamics of cold tandem minns, and constructs it state-space model of which are linear time invariant, using subspace method. Step responses particularly show the influence on mass transfer delay. Input-output data set are obtained form nonlinear differential equations including mass transfer delay and nonlinearity. It is shown that the identified state-apace model well approximates the original systems dynamics.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.90.2-90
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• 2002

A new integral controller is proposed for time-delay plants. The proposed controller has Davison type structure and utilizes a simplified state predictor instead of the optimal state predictor for the extended system. The simplified predictor is introduced by a trick similar to that used in the Smith predictor. As a systematic method for designing the proposed controller, the application of the loop transfer recovery (LTR) technique is considered. For the plant input side and the output side, explicit representations of the sensitivity matrices achieved by enforcing the formal LTR procedure using Riccati equations are obtained. A numerical example is presented to compare the asymptotic...

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.