• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.54-59
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• 2008

A highly accurate wide swing BiCMOS cascode current mirror is proposed. It uses the base-current compensated BJT current mirror. It increases both output impedance and output voltage range by using the npn-NMOS cascode instead of the NMOS-NMOS cascode. The npn transistor copies the input current and the NMOS transistor increases the output impedance for the accurate current mirroring. The proposed current mirror achieves highly constant current for wide output voltage range. Simulation results were verified with measurements performed on a fabricated chip using a 5/16V 0.5um BCD process. It has only $-2.5%{\sim}1.0%$ current error for $0.3V{\sim}16V$ output voltage range.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.51-52
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• 2017

This paper presents an advanced DC droop using both an output current and a grid current. To control parallel-connected converters without communication, the DC droop control is conventionally used. The conventional DC droop control method droops output voltage using an output current. It cannot control the source current causing output voltage errors. This paper proposed the DC droop method using both an output current and a grid current to improve dynamic response of voltage droops. The simulation results with PSIM is provided.

• Journal of Power Electronics
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• v.4 no.2
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• pp.87-95
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• 2004

A new fast-response high-current clamp DC-DC converter circuit design is presented that will meet the requirements and features of the new generation of microprocessors and digital systems. The clamp in the proposed converter amplifies the current in case of severe load changes and is able to produce high slew rate of output current and capability to keep constant the output voltage. This proposed high-current clamp technique is theoretically loss less, low cost and easy to implement with simple control scheme. This is modified from a basic buck topology by replacing the output inductor with two magnetically coupled inductors. Inductors are difference in inductance, one has large inductance and other has small inductance. The inductor with small inductance will take over the output inductor during fast load transient. It speedup the output current slew rate and reduce the output voltage drop in the case of heavy burden load changes.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.395-398
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• 2004

High-linearity voltage-controlled current sources (VCCSs) circuits for wide voltage-controlled oscillator and automatic gun control were proposed. The VCCS consists of emitter follower for voltage input, two common-base amplifier which their emitter connected for current output, and current mirror which connected the two amplifier for large output current. The VCCS used only five transistors and a resistor without an extra bias circuit. Simulation results show that the VCCS has current output range from 0mA to 300mA over the control voltage range from 1V to 4.8V at supply voltage 5V. The linearity error of output current has less than $1.4\%$ over the current range from 0A to 300mA.

• Journal of Power Electronics
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• v.16 no.3
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• pp.840-848
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• 2016

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.

• Journal of international Conference on Electrical Machines and Systems
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• v.1 no.2
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• pp.85-90
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• 2012

This paper presents a topology structure and control method for an input-parallel-output-series(IPOS) inverter system which is suitable for high input current, high output voltage, and high power applications. In order to ensure the normal operation of the IPOS inverter system, the control method should achieve input current sharing(ICS) and output voltage sharing(OVS) among constituent modules. Through the analysis in this paper, ICS is automatically achieved as long as OVS is controlled. The IPOS inverter system is controlled by a three-loop control system which is composed of an outer common-output voltage loop, inner current loops and voltage sharing loops. Simulation results show that this control strategy can achieve low total harmonic distortion(THD) in the system output voltage, fast dynamic response, and good output voltage sharing performance.

• Journal of Power Electronics
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• v.14 no.1
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• pp.135-142
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• 2014

In the design of battery chargers, limiting the output ripple current according to the manufacturer's recommendation is important for reliable service and extended battery life. Ripple components can cause internal heating of the battery and thus reduce the service life of the battery. Care must be exerted in the design of the switching converter for the charge application through the accurate estimation of the output current ripple value. This study proposes a method to reduce the output current ripple of the converter and presents a detailed analysis of the output current ripple of the DC-DC boost converter to provide a guideline for the design of the battery charger.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.347-349
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• 2013

This paper describes analysis and calculation of line frequency ripple current according to output capacitor value and effects of LED connection in the single stage flyback converter with high power factor. The low frequency output ripple current delivered from single stage converter has been analyzed in detail and the method evaluating parasitic resistance included in LED has been provided. In order to verify the equation derived in this paper, the single stage flyback converter has been designed with constant output current regulation with DCM operation. Experiments were conducted with different LED load structures to analyze the effect of LED parasitic resistance on output ripple current. As test results, the calculation can provide guide line to select capacitor values depending on output ripple current and LED characteristics.

• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.255-261
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• 2012

Since PV PCS uses output current sensor for ac output current control, the sensor's sensing value includes unnecessary offset inevitably. If PV inverter is controlled by the included offset value, it's output current will generate DC offset. The DC offset of output current for trans-less PV inverter is fatal to grid, which results in saturating grid side transformer. Usually DSP controller of PV inverter reads several times sensing value during initial operation and, finally, it's average value is used for offset calibration. However, if temperature changes, the offset changes, too. And also, the switch device is not ideal, both each switching element of the voltage drop difference and on & off time delay difference generate DC offset. Thus, to compensate for deadtime and the switch voltage drop, feedback control by output current DC offset should be provided to compensate additional distortion of the output current. The validity of the proposed method is confirmed through PSIM simulation.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.288-290
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• 2006

An efficiency improving method for Uninterruptible Power Supply System(UPS) was developed by using OP-AMP based application circuits such as voltage detection device, current detection device and static switch control device. The efficiency improving algorithm was made by mixing the operating concepts of On-Line type UPS with the operating concepts of Off-Line type UPS. The UPS' inverter does not work if the UPS' output load current is not higher than the low load operating current which is about 0-30(%) of the UPS' output load capacity. The low load operating current is adjustable within the half of the UPS' output load capacity. If the UPS' output load current is rising over than the low load operating current, the UPS' inverter starts working and the inverter output power feeds to the loads of UPS. If UPS' input power breaks out while UPS' inverter does not operate because the load current is low, the inverter starts working within 4(ms) with excessive output voltage which is ${\pm}$8(%) of normal UPS' output voltage. Like these. UPS can continuously feeds power to it's load device and reduce power consumptions.