• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.208-217
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• 2010

This paper presents a novel 10 GHz bio-radar system based on a frequency multiplier and phase-locked loop(PLL) for non-contact measurement of heartbeat and respiration rates. In this paper, a 2.5 GHz voltage controlled oscillator (VCO) with PLL is employed to as a frequency synthesizer, and 10 GHz continuous wave(CW) signal is generated by using frequency multiplier from 2.5 GHz signal. This paper also presents the noise characteristic of the proposed system. As a result, a better performance and economical frequency synthesizer can be achieved with the proposed bio-radar system. The experimental results shows excellent bio-signal measurement up to 100 cm without any additional digital signal processing(DSP), and the proposed system is validated.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.50-55
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• 2008

In this paper, New LC VCO with $8{\sim}10.9$ GHz Band has been designed using commercial $0.35-{\mu}m$ CMOS technology. This proposed circuit is consisted of the parallel construction of the typical NMOS and PMOS cross-coupled pair which is based on the LC tank, MOS cross-coupled pair which has same tail current of complementary NMOS and PMOS, and output buffer. The designed LC VCO, which is according to proposed structure in this paper, takes a 29% improvement of the wide tuning range as 8 GHz to 10.9 GHz, and a 6.48mW of low power dissipation. Its core size is $270{\mu}m{\times}340{\mu}m$ and its phase noise is as -117dBc Hz and -137dBc Hz at 1-MHz and 10-MHz offset, respectively. FOM of the new proposed LC VCO gets -189dBc/Hz at a 1-MHz offset from a 10GHz center frequency. This design is very useful for the 10Gb/s clock generator and data recovery integrated circuit(IC) and SONET communication applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.71-80
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• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.5
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• pp.97-102
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• 2018

In this paper, W-band Waveform Generator for compact radar has been designed and fabricated. DDS (Direct Digital Synthesizer) is applied to generate CW (Continuous Wave) and FMCW (Frequency Modulation Continuous Wave) waveform at high speed. We designed two LO (Local Oscillator) paths for functions of distance delay and distance tracking tests at the prpposed system without extra test equipment. Two mode selections are provided by switch. It is observed that fabricated waveform generator performs -91 dBc/Hz phase noise at offset 1 kHz and -63.2 dBc spurious. Proposed W-band Waveform Generator is expected to apply for W-band compact radar transceiver module.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.470-475
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• 2015

This paper presents a wideband Current-Reused Voltage Controlled Oscillator (VCO) with 2-Step Automatic Amplitude Calibration (AAC). Tuning range of the proposed VCO is from 1.95 GHz to 3.15 GHz. The mismatch of differential voltage is within 0.6 %. At 2.423 GHz, the phase noise is -116.3 dBc/Hz at the 1 MHz offset frequency with the current consumption of 2.6 mA. The VCO is implemented $0.13{\mu}m$ CMOS technology. The layout size is $720{\times}580{\mu}m^2$.