• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.6
• /
• pp.63-70
• /
• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.7-13
• /
• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.12 s.91
• /
• pp.1152-1160
• /
• 2004

OFDM technique was adopted as the standard of IEEE 802.1 la and it has been widely used for wireless LAN, European DVB/DAB system, Korean DMB system. In the standard of IEEE 802.11a the data packet is composed of two parts, preamble and data. Preamble is composed of short pilots and long pilots, which are used for synchronization and estimation of frequency offset and channel. We can also compensate phase noise effect in the transceiver by using above pilots. The phase noise is more complicate than frequency offset and seriously affects system performance. In this paper, we newly propose CPE and ICI simultaneous compensation method to compensate phase noise generated by transceiver oscillator and compare with previous studies. As results, phase noise effect can be significantly compensated by CPE cancellation method, PNS algorithm and our proposed CPE and ICI compensation method. Especially, the proposed CPE and ICI compensation method can achieve the best BER performance compared with original OFDM, CPE cancellation method and PNS algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.10
• /
• pp.3866-3872
• /
• 2010

This paper presents a design of high power oscillator using a spiral resonator and high power transistor with measurement. Even lots of drawbacks are known in design of oscillators using high power transistors, the spiral resonator is adopted because it has relatively high Q out of planar resonators. The designed power oscillator at 1.8GHz is fabricated and tested. Measurement shows the obtained output power is 23.5dBm at 1.74GHz with -146.76dBc/Hz of phase noise at 1MHz offset. In addition, it is illustrated that the frequency stability is excellent with the shift less than 1MHz and the measured maximum output power is around 24dBm when the bias voltages are adjusted.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.10A
• /
• pp.971-978
• /
• 2005

In this paper, we design and fabricate a VCO(Voltage Controlled Oscillator) for radar detector of X/K/Ka band using frequency multiplier. The existing VCO operated in radar detector have many Problems such as narrow bandwidth, slow frequency variable rate, unstable of production due to high frequency. So we design and fabricate a VCO improved such problems using frequency multiplier. As a result of measure, investigated frequency multiple VCO show its output power 3.64 dBm at multiplied operating frequency 11.27 GHz and have wide frequency tuning range of 660 MHz by controlled voltage 0V to 4.50 V applied diode. And also its phase noise is -104.0 dEc at 1 MHz offset frequency so we obtain suitable performance for commercial use.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• v.9 no.2
• /
• pp.869-872
• /
• 2005

This paper presents a new switchable dual mode VCO(Voltage-Controlled Oscillator). The VCO is efficient in dual mode operation and has self-bias adjustment based on the operation frequencies of 2.4 GHz and 5 GHz. The switching is done using MOS transistors and tuning is done using MOS varactors. It is implemented using TSMC 0.18${\mu}$m CMOS technology. It is powered by 1.8V supply. The measured results showed that the overall tuning range is approximately 13% at 5 GHz and 8% at 2.4 GHz. The measured phase noise is approximately -102 dBc/Hz at 1 MHz offset for 5 GHz and -89 dBc/Hz at 600kHz offset for 2.4 GHz. The VCO showed tail currents of 2mA in 5GHz mode and 2.5mA in 2.4GHz mode from a 1.8 V supply, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.5
• /
• pp.715-722
• /
• 2000

In this paper, the PLDRO is designed and implemented for X-band. It is comprised of tunable high Q resonator with a varactor diode for frequency tuning, loop filter and a 1/8 prescaler which up to 10GHz. Also, it is implemented a TCXO and a VCO signal into the phase detector and achieved a highly stable signal source. From the measurement, the designed PLDRO has the output power of 2.5dBm at 8GHz and phase noise of -64.33dBc at 10KHz offset from carrier. Its characteristic is 26 dBc. This PLDRO has much better temperature stability.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.4
• /
• pp.715-720
• /
• 2012

This study presents a hybrid balanced voltage controlled oscillator (VCO) circuit which is suitable for low phase noise operation at sub-1V supply voltages. Half circuits of the proposed VCO use the varactor-integrated feedback capacitors in their respective circuit. The varactor-integrated feedback capacitors further increase the negative resistance of the equivalent tank thereby ensuring stable start-up of oscillation even at the sub-1V supply voltage. In addition, this work theoretically analyses the phenomenon of the increase of the negative resistance. Simulation results using a $0.18{\mu}m$ RF CMOS technology exhibit the phase noises of -122.4 to -125.5.8 dBc/Hz at 1 MHz offset from oscillation frequency of 4.87 GHz over the supply voltages of 0.6 through 0.9 V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.7
• /
• pp.7-15
• /
• 2002

The digital DBS tuner is designed and implemented in a CMOS process using a direct-conversion architecture that offers a high degree of integration. To generate mathched LO I/Q quadrature signals covering the total input frequency range, a fully integrated ring oscillator is employed. And, to decrease a high level of phase noise of the ring oscillator, a frequency synthesizer is designed using a double loop strucure. This paper proposes and verifies a band selective loop for fast frequency switching time of the double loop frequency synthesizer. The down-conversion mixer with source follower input stages is used for low voltage operation. An experiment implementation of the frequency synthesizer and mixer with integrated a 0.25um CMOS process achieves a switching time of 600us when frequency changes from 950 to 2150MHz. And, the experiment results show a quadrature amplitude mismatch of max. 0.06dB and a quadrature phase mismathc of max. >$3.4^{\circ}$.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.4 no.2 s.7
• /
• pp.81-87
• /
• 2005

In this paper, a VCDRO(Voltage Control Dielectirc Resonator Oscillator) for signal source of doppler radar system is designed and fabricated. The proposed VCDRO is made with new tuning mechanism using CPW line. The coplanar waveguide of $\lambda_{g}$/2 in length with varactor diode is placed on the metallization side under the dielectric resonator and coupled to it. Tuning varactor diode is mounted at one end of the CPW. The proposed circuit tuned by a CPW allows one more varactor diode to be mounted on the optimized CPW, where a greater sensitivity of frequency tuning is needed. With varying the biasing voltage for the varactor diode from 0 V to 15 V, output frequency tuning of 12 MHz is obtained. The PLDRO exhibits output power of 16.5 dBm with phase noise in the phase locked state characteristic of -115 dBc/Hz at 100 Hz, -105 dBc/Hz at the 10 kHz, and -102 dBc/Hz at 1 Hz offset from 10.525 GHz , respectively.