• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.933-940
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• 2017

A wireless power transfer system with a negative impedance converter(NIC) was designed and tested. The system was investigated to identify the effects of ferrites and conductors. To improve the power transfer efficiency(PTE), the Q-factor of the transmitter was enhanced by the negative resistance generated by the NIC. The NIC was composed of an Op-Amp and resistors. The negative resistance was obtained with respect to a resistor connected in a feedback loop. The dimension of the Tx coil was $250mm{\times}250mm{\times}0.8mm$. The impedance and Q-factor were $31+j1874{\Omega}$ and 60, respectively. The negative resistance was selected to be $30{\Omega}$, and the Q-factor was increased to 900 by reduction of the transmitter resistance, which was about 15 times higher than that of a conventional transmitter. The measured PTE was greatly improved in comparison to that of a conventional system. These results demonstrate that the PTE is enhanced by using the NIC.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.10
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• pp.629-636
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• 2016

This study presents the development of an acid resistance velocity sensor that is used for measuring velocity inside a copper sulfate plating bath. First, researchers investigated the acid resistance coating to confirm the suitability of the anti-acid sensor in a very corrosive environment. Then, researchers applied signal processing methods to reduce noise and amplify the signal. Next, researchers applied a pressure-resistive sensor with an operation amplifier (Op Amp) and low-pass filter with high impedance to match the output voltage of a commercial flowmeter. Lastly, this study compared three low-pass filters (Bessel, Butterworth and Chebyshev) to select the appropriate signal process circuit. The results show 0.0128, 0.0023, and 5.06％ of the mean square error, respectively. The Butterworth filter yielded more precise results when compared to a commercial flowmeter. The acid resistive sensor is capable of measuring velocities ranging from 2 to 6 m/s with a 2.7％ margin of error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.56-63
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• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• Annals of Clinical Neurophysiology
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• v.13 no.2
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• pp.80-86
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• 2011

Background: A dry-type electrode is an alternative to the conventional wet-type electrode, because it can be applied without any skin preparation, such as a conductive electrolyte. However, because a dry-type electrode without electrolyte has high electrode-to-skin impedance, an impedance-converting amplifier is typically used to minimize the distortion of the bioelectric signal. In this study, we developed an active dry electroencephalography (EEG) electrode using an impedance converter, and compared its performance with a conventional Ag/AgCl EEG electrode. Methods: We developed an active dry electrode with an impedance converter using a chopper-stabilized operational amplifier. Two electrodes, a conventional Ag/AgCl electrode and our active electrode, were used to acquire EEG signals simultaneously, and the performance was tested in terms of (1) the electrode impedance, (2) raw data quality, and (3) the robustness of any artifacts. Results: The contact impedance of the developed electrode was lower than that of the Ag/AgCl electrode ($0.3{\pm}0.1$ vs. $2.7{\pm}0.7\;k{\Omega}$, respectively). The EEG signal and power spectrum were similar for both electrodes. Additionally, our electrode had a lower 60-Hz component than the Ag/AgCl electrode (16.64 vs. 24.33 dB, respectively). The change in potential of the developed electrode with a physical stimulus was lower than for the Ag/AgCl electrode ($58.7{\pm}30.6$ vs. $81.0{\pm}19.1\;{\mu}V$, respectively), and the difference was close to statistical significance (P=0.07). Conclusions: Our electrode can be used to replace Ag/AgCl electrodes, when EEG recording is emergently required, such as in emergency rooms or in intensive care units.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).