• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.248-251
• /
• 2017

In this paper, The proposed board is developed by EMI compliant Dash Camera with $360^{\circ}$ omni angle. The proposed board is designed by designing DM and CM input noise reduction circuit and applying active EMI filter coupling circuit. The DM and CM input noise reduction circuit design uses a differential op amp circuit to obtain the DM noise coupled to the input signal via the parasitic capacitance(CP). In order to simplify the circuit by applying the active EMI filter coupling circuit, a noise separator is installed to compensate the noise of the EMI source to compensate the CM and DM active filter simultaneously. In order to evaluate the performance of the board for the proposed EMI response, an authorized accreditation body has confirmed that the electromagnetic certification standard for each frequency band is satisfied.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.5
• /
• pp.49-55
• /
• 2016

To separate the CM and DM noise in the EMI generated in various electrical electronic systems, passive and active separators have been researched. These separators are an important part of an effective active EMI-filter. The passive separator has some advantages, in that it is easy to realize at a low price and its structure is very simple. However, its major drawback is that its accurate inductor realization and accurate core selection are very difficult. The active separator is smaller in size and more accurate, but its main drawback is that an op-amp which has a broad band frequency response is necessary, its cost is high, and a DC power circuit is required. This paper compares the characteristics of EMI filters which apply the existing passive separator and proposed active separator. It was concluded that an active separator is needed for expensive and accurate equipment, whereas a passive separator is sufficient for inexpensive and general purpose EMI filters.

• Journal of Convergence for Information Technology
• /
• v.11 no.8
• /
• pp.1-7
• /
• 2021

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.12
• /
• pp.77-84
• /
• 1998

A voltage controlled chaotic circuit has been designed in integrated circuit and fabricated by using 0.8$\mu\textrm{m}$ single poly CMOS technology. The fabricated chaotic circuit consist of sample and hold circuits, op-amps, nonlinear function generator and two phase clock generator. The test results of the chaotic circuit show that periodic state, quasi-periodic state and chaotic state can be obtained according to the input control voltage with the ${\pm}$2.5V power supply and clock rate of 20kHz. In addition, two dimensional chaotic patterns have been observed by connecting this circuit in parallel or series

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.8
• /
• pp.1386-1391
• /
• 2000

In this paper, the method to linearize the non-linearity of diode and to compensate the characteristics change of diode with the temperature is studied. Square root circuit is used to linearize the non-linearity of diode about the input power, and two identical diodes and OP-Amps, which have variable reference, are used to compensate the characteristic change of diode with the temperature. As the result, designed diode power detector (with the square root circuit and temperature compensation circuit) can detect the output power linearly with the 0.23 $\pm$0.025V/dBm rate in the case the input power is greater than -6 dBm, and the designed circuit operates stably with no variation in the output data about the temperature change from the room temperature to 8$0^{\circ}C$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.3
• /
• pp.678-684
• /
• 2013

This paper describes a low-power baseband circuit for SAW-less LTE-Advanced transmitters. The proposed transmitter baseband circuit consists of a 2nd-order Tow-Thomas type active RC-LPF and a 1st-order passive RC LPF. It can provide a 7 multi-channel cut-off frequencies and wide gain control range of -41 dB ~ 0 dB with a 1-dB step. The proposed 2nd-order active RC-LPF adopts an op-amp in which three other sub-op amps are in parallel connected to reduce DC current for different cutoff frequency. In addition, each sub-op amp adopts both Miller and feed-forward phase compensation method to achieve an UGBW of more than 1-GHz with a small DC power consumption. The proposed baseband circuit is implemented in 65-nm CMOS technology, consuming DC power from 6.3 mW to 24.1 mW from a 1.2V supply voltage for each different cut-off frequency.

• Journal of Sensor Science and Technology
• /
• v.6 no.2
• /
• pp.137-144
• /
• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Proceedings of the KIEE Conference
• /
• 1995.07c
• /
• pp.1120-1122
• /
• 1995

This paper presents a 2-stage, simple, power-efficient 3V CMOS operational amplifier and its equation based design optimization. Because of its simple structure, it is very suitable as a VLSI library cell in analog/digital mixed-mode systems. The op-amp, which contains a constant-$g_m$ rail-to-rail input stage and a simple feedforward class-AB rail-to-rail output stage, is analyzed and the results are presented in the form of design equations and procedures, which provide an insight into the trade-offs among performance requirements. The results of SPICE simulations are shown to agree very welt with the use of design equations.

• ETRI Journal
• /
• v.29 no.2
• /
• pp.212-218
• /
• 2007

A novel low-voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail-to-rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ${\pm}0.75V$ with a total standby current of 304 ${\mu}A$. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ${\pm}1$ mA. An application of the CFOA to realize a new all-pass filter is given. PSpice simulation results using 0.25 ${\mu}m$ CMOS technology parameters for the proposed CFOA and its application are given.

• 제어로봇시스템학회:학술대회논문집
• /
• 1996.10a
• /
• pp.389-392
• /
• 1996

We propose a method to improve repeatability positioning precision of a linear pulse motor. By using this method the systematic error which may make the precision worse can be suppressed easily. And also we show that Power OP-Amp drive system enables the accidental error to be suppressed in comparison with PWM control drive system using IGBT inverter. As a result of the suppression of systematic and accidental error, improved performance of a linear pulse motor with repetitive positioning control is shown by experimental results.