• 한국정밀공학회지
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• 제22권2호
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• pp.60-69
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• 2005

In electrostatic suspension system of thin plates like a silicon wafer or an aluminum disk for hard disk applications, the lateral restoring force exerted on a suspended object plays an important role since the lateral motion of the suspended object, owing to the inherently stable restoring forces, can be passively stabilized without any active control of it. This paper reports about the measurement apparatus of the lateral restoring force originating from a relative translation of the suspended object with respect to the electrodes-for-suspension. An approximate calculation of the lateral force in disk-shaped objects, the structure of the measurement apparatus, a measurement method, stabilization condition and the guideline in designing the measurement apparatus are described. Experimental results obtained by using a 3.5-inch aluminum disk as a suspended object are presented as well in order to assess the magnitude of lateral force and stiffness, and also verify the usefulness of the measurement apparatus.

• Applied Microscopy
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• 제52권
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.95-100
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• 2006

The GaAs-on-insulator (GOI) wafer fabrication technique has been developed by using ion-cut process, based on hydrogen ion implantation and wafer direct bonding techniques. The hydrogen ion implantation condition for the ion-cut process in GaAs and the associated implantation mechanism have been investigated in this paper. Depth distribution of hydrogen atoms and the corresponding lattice disorder in (100) GaAs wafers produced by 40 keV hydrogen ion implantation were studied by SIMS and RBS/channeling analysis, respectively. In addition, the formation of platelets in the as-implanted GaAs and their microscopic evolution with annealing in the damaged layer was also studied by cross-sectional TEM analysis. The influence of the ion fluence, the implantation temperature and subsequent annealing on blistering and/or flaking was studied, and the optimum conditions for achieving blistering/splitting only after post-implantation annealing were determined. It was found that the new optimum implant temperature window for the GaAs ion-cut lie in $120{\sim}160^{\circ}C$, which is markedly lower than the previously reported window probably due to the inaccuracy in temperature measurement in most of the other implanters.

• 한국전기전자재료학회논문지
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• 제15권11호
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• pp.953-957
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• 2002

Single crystal 3C-SiC (cubic silicon carbide) thin-films were deposited on Si(100) wafer up to the thickness of 4.3 ${\mu}{\textrm}{m}$ by APCVD (atmospheric pressure chemical vapor deposition) method using HMDS (hexamethyildisilane; ｛CH$_{3}$｝$_{6}$ Si$_{2}$) at 135$0^{\circ}C$. The HMDS flow rate was 0.5 sccm and the carrier gas flow rate was 2.5 slm. The HMDS flow rate was important to get a mirror-like crystal surface. The growth rate of the 3C-SiC film was 4.3 ${\mu}{\textrm}{m}$/hr. The 3C-SiC epitaxial film grown on Si(100) wafer was characterized by XRD (X-ray diffraction), AFM (atomic force microscopy), RHEED (reflection high energy electron diffraction), XPS (X-ray photoelecron spectroscopy), and Raman scattering, respectively. Two distinct phonon modes of TO (transverse optical) near 796 $cm^{-1}$ / and LO (longitudinal optical) near 974$\pm$1 $cm^{-1}$ / of 3C-SiC were observed by Raman scattering measurement. The heteroepitaxially grown film was identified as the single crystal 3C-SiC phase by XRD spectra (2$\theta$=41.5。).).

• 마이크로전자및패키징학회지
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• 제22권3호
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• pp.19-23
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• 2015

본 연구에서는 COG (Chip On Glass) 패키지 적용을 위해 Au 범프를 전기도금 공정을 사용하여 Al/Si wafer와 SiN/Si wafer 위에 TiW/Au 구조를 갖는 두 종류의 Au범프 시료를 제작하였다. UBM (Under Bump Metallurgy) 물질로서 TiW 박막을 스퍼터링 방법으로 증착하였으며 스퍼터링 입력 파워(500~5000 Watt)에 따른 박리 현상을 관찰하였다. 안정된 계면 접착을 나타내는 스퍼터링 파워는 1500 Watt임을 확인 할 수 있었다. 또한 SAICAS (Surface And Interfacial Cutting Analysis System) 장비를 사용하여 기판 종류에 따른 Au Bump의 접착력을 조사하였다. TiW 증착 조건은 스퍼터링 파워를 1500 Watt로 고정하였다. TiW/Au 계면의 접착력은 두 종류의 wafer (Al/Si과 SiN/Si wafers)에 관계없이 오차 범위 안에서 비슷한 접착력을 보여주었으나, TiW UBM 스퍼터링 박막 계면에서의 접착력은 하부 박막인 Al 금속과 SiN 비금속 박막에서의 접착력 차이가 약 2.2배 크게 나타났다. 즉, Al/Si wafer와 SiN/Si wafer위에 증착된 TiW의 접착력은 각각 0.475 kN/m와 0.093 kN/m 값을 나타내었다.

• 한국진공학회지
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• 제10권3호
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• pp.361-367
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• 2001

CMP(Chemical Mechanical Polishing)는 반도체 소자 제조공정 중 다층 배선구조의 평탄 경면화에 널리 이용되고 있다. 차세대 웨이퍼로 각광받는 SOI(Silicon On Insulator) 웨이퍼 제조공정 중 웨이퍼 표면 미소 거칠기를 개선하기 위해서 본 논문에서는 여러 가지 가공변수(슬러리와 연마패드)에 따른 CMP 연마능률과 표면 미소 거칠기 변화에 대해 연구하였다. 결과적으로 연마능률은 슬러리의 입자 크기가 증가할수록 이에 따라 증가하였으며, 미소 거칠기는 슬러리의 연마입자보다는 연마패드에 영향이 더욱 지배적이다. AFM(Atomic Force Microscope)에 의한 평가에서 표면 미소 거칠기가 27 $\AA$ Rms에서 0.64 $\AA$ Rms로 개선됨을 확인할 수 있었다.

• 한국전기전자재료학회논문지
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• 제23권5호
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• pp.358-363
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• 2010

The polishing pad is important element for polishing characteristic such as material removal rate(MRR) and within wafer non-uniformity(WIWNU) in the chemical mechanical planarization(CMP). The result of the viscoelasticity measurement shows that 1st elastic modulus is increased and 2nd elastic modulus is decreased when the top pad is thickened. The finite element analysis(FEA) was conducted to predict characteristic of polishing behavior according to the pad thickness. The result of polishing experiment was similar with the FEA, and it shows that the 1st elastic modulus affects instantaneous deformation of pad related to MRR. And the 2nd elastic modulus has an effect on WIWNU due to the viscoelasticity deformation of pad.

• 한국광학회지
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• 제14권5호
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• pp.504-508
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• 2003

최근 전자산업계에 새롭게 널리 생산되는 마이크로 전자부품들은 왜곡이 최소화된 정밀한 외관 형상을 갖도록 제조되고 관리되지만, 측정 대상의 표면이 가시광 영역에서 광산란되는 특징을 가짐으로 인해, 기존의 피죠나 마이켈슨 형태의 비교간섭법으로는 고정밀의 삼차원 형상측정이 용이하지 아니하였다. 본 논문에서는 광섬유를 이용한 새로운 개념의 점회절 간섭계를 제안하고, 이를 광산란 거친표면의 대표적인 제품인 칩패키지와 실리콘 웨이퍼의 삼차원 형상 측정에 적용하였다. 측정결과 66 mm 측정영역에서 측정 형상오차 PV(peak-to-valley value) 5.6 $\mu\textrm{m}$, 분산값($\sigma$) 1.5 $\mu\textrm{m}$를 획득함으로써 기존의 비교 간섭 측정법에 비해 더욱 향상된 측정 정밀도를 획득하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.346.2-346.2
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• 2016

The rear side contact recombination in the crystalline silicon solar cell could be reduced by back surface field. We formed polycrystalline silicon as a back surface field through crystallization of amorphous silicon. A thin silicon oxide applied to the passivation layer. We used quasi-steady-state photoconductance measurement to analyze electrical properties with various annealing condition. And, blister formed on surface of wafer during the annealing process. We observed the blister after varied annealing process with wafer of various surface. Shape and density of blister is influenced by various annealing temperature and process time. As the annealing temperature became higher, the average diameter of blister is decreased and total number of blister is increased. The sample with the $600^{\circ}C$ annealing temperature and 1 min annealing time exhibited the highest implied open circuit voltage and lifetime. We predicted that the various shape and density of blister affects the lifetime and implied open circuit voltage.

• 전자공학회논문지A
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• 제31A권7호
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• pp.76-84
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• 1994

The characteristics of 3 inch wafer scale GaAs epitaxial wafer grown by molecular beam epitaxy for LSI process application were studied. The thickness and doping uniformity are characterized and discussed. The growth temperature and growth rate were $600^{\circ}C$ by pyrometer, and 1 $\mu$m/h, respectively. It was found that thickness and doping uniformity were 3.97% and 4.74% respectively across the full 3 inch diameter GaAs epitaxial layer. Also, ungated MESFETs have been fabricated and saturation current measurement showed 4.5% uniformity on 3 inch, epitaxial layer, but uniformity of threshold voltage increase up to 9.2% after recess process for MESFET device.