• 전자공학회논문지
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• 제49권9호
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• pp.259-269
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• 2012

전원 전압이 낮아지고, 칩의 동작 속도가 빨라짐에 따라 온-칩 인덕턴스를 포함한 power distribution network (PDN) 분석이 중요해 질 것으로 예측된다. 본 논문에서는 일반적인 온-칩 전력 격자 구조에 적용시킬 수 있는 효과적인 인덕턴스 추출방법에 대해 제안한다. Chip layout에 적용할 수 있는 loop 인덕턴스 모델을 제시하고, 그 모델을 사용하여 post layout RC extraction netlist로 부터 인덕턴스를 포함한 netlist를 추출할 수 있는 tool을 개발하였다. 제안된 loop 인덕턴스 모델과 개발된 tool의 정확성은 회로 simulation을 통해 PEEC 모델과 비교하여 검증하였다. 인덕턴스 추출 방법을 실제 chip layout에 적용시켜 on-chip inductance를 포함한 PDN의 voltage fluctuation을 예측하였다. 패키지와 PCB 모델을 포함한 co-simulation 모델을 구성하여 on-chip inductance의 영향을 분석하였다.

• Nuclear Engineering and Technology
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• 제53권10호
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• pp.3327-3334
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• 2021

Present electric grids are advanced to integrate smart grids, distributed resources, high-speed sensing and control, and other advanced metering technologies. Cybersecurity is one of the challenges of the smart grid and nuclear plant digital system. It affects the advanced metering infrastructure (AMI), for grid data communication and controls the information in real-time. The research article is emphasized solving the nuclear and smart grid hardware security issues with the integration of field programmable gate array (FPGA), and implementing the latest Time Authenticated Cryptographic Identity Transmission (TACIT) cryptographic algorithm in the chip. The cryptographic-based encryption and decryption approach can be used for a smart grid distribution system embedding with FPGA hardware. The chip design is carried in Xilinx ISE 14.7 and synthesized on Virtex-5 FPGA hardware. The state of the art of work is that the algorithm is implemented on FPGA hardware that provides the scalable design with different key sizes, and its integration enhances the grid hardware security and switching. It has been reported by similar state-of-the-art approaches, that the algorithm was limited in software, not implemented in a hardware chip. The main finding of the research work is that the design predicts the utilization of hardware parameters such as slices, LUTs, flip-flops, memory, input/output blocks, and timing information for Virtex-5 FPGA synthesis before the chip fabrication. The information is extracted for 8-bit to 128-bit key and grid data with initial parameters. TACIT security chip supports 400 MHz frequency for 128-bit key. The research work is an effort to provide the solution for the industries working towards embedded hardware security for the smart grid, power plants, and nuclear applications.

• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.1-6
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• 2017

As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

• Journal of Power Electronics
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• 제13권2호
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• pp.313-321
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• 2013

This paper describes the operation analysis results of a communication-based DC micro-grid using a hardware simulator developed in the lab. The developed hardware simulator is composed of distributed generation devices such as wind power, photovoltaic power and fuel cells, and energy storage devices such as super-capacitors and batteries. Whole system monitoring and control was implemented using a personal computer. The power management scheme was implemented in a main controller based on a TMS320F28335 chip. The main controller is connected with the local controller in each of the distributed generator and energy storage devices through the communication link based on a CAN or an IEC61850. The operation analysis results using the developed hardware simulator confirm the ability of the DC micro-grid to supply the electric power to end users.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.707-710
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• 2005

This paper presents a 3kW grid-connection photovoltaic power generation system and its topology. Photovoltaic system must provide the sinusoidal output voltage wave for unity power factor High frequency switching converters are becoming more popular because of several benefits which are essential in power conversion system. This paper introduces a high speed digital controller using TMS320F2812 DSP chip which can be used for high frequency switching converters. The experimental results of the proposed PWM Inverter demonstrates its high performance with unity input power factor having very low distorsion in input current waveforms and good dynamic characteristics at full load.

• 신재생에너지
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• 제3권4호
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• pp.69-76
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• 2007

In this paper, a PV multi-string PCS with a grid-connection is proposed. An improved MPPT algorithm for the PV multi-string PCS is suggested. Each PV string has its own MPP tracker and the proposed MPPT algorithm prevents LMPP tracking due to power ripple. In the PV PCS with single-phase inverter has a large current ripple at twice the grid frequency. The current ripple reduction algorithm without external component is suggested. Also, this paper proposes a simple control method to achieve sharing of the PV string voltage and current among the interleaved parallel boost converters. All algorithms and controllers are implemented on a single-chip microcontroller. Experimental results obtained on a 3kW prototype show high performance of the proposed PV multi-string PCS.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.255-258
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• 2007

In this paper, a PV multi-string PCS with a grid-connection is proposed. An improved MPPT algorithm for the PV multi-string PCS is suggested. Each PV string has its own MPP tracker and the proposed MPPT algorithm prevents LMPP tracking due to power ripple. In the PV PCS with single-phase inverter has a large current ripple at twice the grid frequency. The current ripple reduction algorithm without external component is suggested. Also, this paper proposes a simple control method to achieve sharing of the PV string voltage and current among the interleaved parallel boost converters. All algorithms and controllers are implemented on a single-chip microcontroller. Experimental results obtained on a 3kW prototype show high performance of the proposed PV multi-string PCS.

• 전기학회논문지
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• 제59권11호
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• pp.1964-1970
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• 2010

A new intelligent power network (Smart Grid) that grafts some new technologies, such as the extension of the new and reproducible energy, electric motors, and electric storages, onto the regulation of green house gases according to the recent convention on climate changes has been actively promoted. As establishing such an intelligent power network, it is possible to implement a real-time rate system according to the change from the conventional single directional information transmission to the bidirectional information transmission. Such a real-time rate system can provide power during the chip rate hour by avoiding the high rate hour although customers use the same level of power through providing such real-time rate information including power generation costs. In this study, the establishment of an operating system that makes an effective use of the real-time rate system and its operation method are to be proposed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.