• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.251-258
• /
• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.8
• /
• pp.54-61
• /
• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.242-242
• /
• 2006

Increasingly complex tasks are performed by computers or cellular phone, requiring more and more memory capacity as well as faster and faster processing speeds. This leads to a constant need to develop more highly integrated circuit systems. Therefore, there have been numerous studies by many engineers investigating circuit patterning. In particular, PCB including module/package substrates such as FCB (Flip Chip Board) has been developed toward being low profile, low power and multi-functionalized due to the demands on miniaturization, increasing functional density of the boards and higher performances of the electric devices. Imprint lithography have received significant attention due to an alternative technology for photolithography on such devices. The imprint technique. is one of promising candidates, especially due to the fact that the expected resolution limits are far beyond the requirements of the PCB industry in the near future. For applying imprint lithography to FCB, it is very important to control thermal properties and mechanical properties of dielectric materials. These properties are very dependent on epoxy resin, curing agent, accelerator, filler and curing degree(%) of dielectric materials. In this work, the epoxy composites filled with silica fillers and cured with various accelerators having various curing degree(%) were prepared. The characterization of the thermal and mechanical properties wasperformed by thermal mechanical analysis (TMA), thermogravimetric analysis (TGA), differential scanning calorimetry (DSC), rheometer, an universal test machine (UTM).

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.1
• /
• pp.64-72
• /
• 2013

Recently, stream cipher Rabbit was selected for the final eSTREAM portfolio organized by EU ECRYPT and as one of algorithm in part of ISO/IEC 18033-4 Stream Ciphers on ISO Security Standardization. However, a feasibility of practical power analysis attack to algorithm in experiment was introduced. Therefore, we propose appropriate methods such as random masking and hiding schemes to secure against power analysis attack on stream cipher Rabbit. We implement the proposed method with increment of 24% operating time and 12.3% memory requirements due to maintaining a high-speed performance. We use a 8-bit RISC AVR microprocessor (ATmegal128L chip) to implement our method for practical experiments, and verify that stream cipher Rabbit with our method is secure against power analysis attack.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.1
• /
• pp.92-99
• /
• 2005

In this paper, we present a high-level design methodology applied on a network system-on-a-chip(SOC) using SystemC. The main target of our approach is to get optimum performance parameters for high network address translation(NAT) throughput. The Fast Ethernet media access controller(MAC) and its direct memory access(DMA) controller are modeled with SystemC in transaction level. They are calibrated through the cycle-based measurement of the operation of the real Verilog register transfer language(RTL). The NAT throughput of the model is within $\pm$10% error compared to the output of the real evaluation board. Simulation speed of the model is more than 100 times laster than the RTL. The validated models are used for intensive architecture exploration to find the performance bottleneck in the NAT router.

• Journal of the Institute of Convergence Signal Processing
• /
• v.11 no.3
• /
• pp.244-249
• /
• 2010

The design of error correction code with low complexity has a good attraction for next generation multi-level cell flash memory. Sharing sub-expressions is effective method to reduce complexity and chip size. This paper proposes a new design method of m-bit parallel BCH encoder based on serial linear feedback shift register structure with low complexity using sub-expression. In addition, general algorithm for obtaining the sub-expression is introduced. The sub-expression can be expressed by matrix operation between sub-matrix of generator matrix and sum of two different variables. The number of the sub-expression is restricted by. The obtained sub-expressions can be shared for implementation of different m-parallel BCH encoder. This paper is not focused on solving a problem (delay) induced by numerous fan-out, but complexity reduction, expecially the number of gates.

• Proceedings of the KIEE Conference
• /
• 2006.07c
• /
• pp.1438-1439
• /
• 2006

$Ge_{2}Sb_{2}Te_5$(GST) thin film at present is a promising candidate for a phase change random access memory (PCRAM) based on the difference in resistivity between the crystalline and amorphous phase. PCRAM is an easy to manufacture, low cost storage technology with a high storage density. Therefore today several major chip in manufacturers are investigating this data storage technique. Recently, A. Pirovano et al. showed that PCRAM can be safely scaled down to the 65 nm technology node. G. T Jeonget al. suggested that physical limit of PRAM scaling will be around 10 nm node. Etching process of GST thin ra films below 100 nm range becomes more challenging. However, not much information is available in this area. In this work, we report on a parametric study of ICP etching of GST thin films in $Cl_2$/Ar chemistry. The etching characteristics of $Ge_{2}Sb_{2}Te_5$ thin films were investigated using an inductively coupled plasma (ICP) of $Cl_2$/Ar gas mixture. The etch rate of the GST films increased with increasing $Cl_2$ flow rate, source and bias powers, and pressure. The selectivity of GST over the $SiO_2$ films was higher than 10:1. X-ray photoelectron spectroscopy(XPS) was performed to examine the chemical species present in the etched surface of GST thin films. XPS results showed that the etch rate-determining element among the Ge, Sb, and Te was Te in the $Cl_2$/Ar plasma.

• Journal of Advanced Navigation Technology
• /
• v.17 no.5
• /
• pp.560-567
• /
• 2013

In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.21 no.5
• /
• pp.35-45
• /
• 2011

The Salsa20/12 stream cipher selected for the final eSTREAM portfolio has a better performance than software implementation of AES using an 8-bit microprocessor with restricted memory space, In the theoretical approach, the evaluation of exploitable timing vulnerability was 'none' and the complexity of side-channel analysis was 'low', but there is no literature of the practical result of power analysis attack. Thus we propose the correlation power analysis attack method and prove the feasibility of our proposed method by practical experiments, We used an 8-bit RISC AVR microprocessor (ATmegal128L chip) to implement Salsa20/12 stream cipher without any countermeasures, and performed the experiments of power analysis based on Hamming weight model.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.49 no.4
• /
• pp.1-9
• /
• 2012

LCD(Liquid Crystal Display) commonly used as an output device has a drawback of slow response time compared with CRT display. This drawback causes motion blur especially when an abrupt intensity change occurs in an image sequence as time goes on. To overcome the problem of slow response time overdriving technique has been used in TCON of LCD. In this technique, the previous frame data has to be compressed and stored in an external memory. Considering both chip size of TCON and computational complexity, AM-BTC has been applied to the 8bit HD display driver. However, the conventional method is not suitable for 10 bit Full HD because 10 bit Full HD data is much larger than that of 8 bit HD data. Being applied to 10 bit Full HD display driver, the conventional method increase cost by enlarging the external memory size of TCON or deteriorates image quality. In this paper, we propose dual BTC image coding technique for Full HD display driver that is an adaptive coding scheme according to morphological information of each sample block. Through experiments, it is verified that the proposed Dual BTC method performs better than the conventional method not only quantitatively but also qualitatively.