• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.867-869
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• 2008

We have investigated the effects of hydrogen plasma treatment by PECVD (Plasma Enhanced Chemical Vapor Deposition) in the back channel region, the method for reducing the off state leakage current which increases with the short channel length of a-Si:H TFTs. To improve the off current characteristics, we analyzed the hydrogen plasma treatment with various RF power and plasma treatment times of PECVD. As the result of hydrogen plasma treatment in the back channel region it was remarkably reduced the off current level of 2um channel length TFT.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.2
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• pp.181-184
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• 2017

This study analyzes the turn-on and turn-off transients of a metal-oxide-semiconductor field-effect transistor (MOSFET) with high-switching frequency systems. In these systems, the voltage distortion becomes serious at the output terminal of a Vienna rectifier by the turn-off delay of the MOSFET. The current has low-order harmonics through this voltage distortion. This paper describes the transient of the turn-off that causes the voltage distortion. The algorithm for reducing the sixth harmonic using a proportional-resonance controller is proposed to improve the current distortion without complex calculation for compensation. The reduction of the current distortion by high-switching frequency is verified by experiment with the 2.5-kW prototype Vienna rectifier.

• Proceedings of the KSME Conference
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• 2001.06a
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• pp.529-533
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• 2001

NDI technique system using AC current is newly developed for inspection of defects. This technique is non-contact measurement system and can be applied for locating and sizing of surface defects in components. In this paper, the technique was applied for evaluating the location and size for 2-dimensional surface cracks and we had investigated the influence of frequency and lift-off. The results show that defects are able to detect with the variety of voltage, and the measuring voltage for the depth of defects are under the influence of the measuring frequency and the lift-off.

• Nuclear Engineering and Technology
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• v.54 no.2
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• pp.501-506
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• 2022

Long turn-off time limits high frequency operation of Bipolar Junction Transistors (BJTs). Turn-off time decreases with increases in the recombination rate of minority carriers at switching transients. Fast neutron irradiation on a Si BJT incurs lattice damages owing to the displacement of silicon atoms. The lattice damages increase the recombination rate of injected holes with electrons, and decrease the hole lifetime in the base region of pnp Si BJT. Fast neutrons generated from a beryllium target with 30 MeV protons by an MC-50 cyclotron were irradiated onto pnp Si BJTs in experiment. The experimental results show that the turn-off time, including the storage time and fall time, decreases with increases in fast neutron fluence. Additionally, it is confirmed that the base current increases, and the collector current and base-to-collector current amplification ratio decrease due to fast neutron irradiation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.869-872
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• 2006

In this paper, the threshold voltage roll-off been analyzed for nano structure double gate FinFET. The analytical current model has been developed , including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel- framers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off Is very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1298-1305
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• 2016

This paper presents the development of a short-circuit protection mechanism on a high voltage switch (HVS) board which is built by a series connection of semiconductor switches. The HVS board is able to quickly detect and limit the peak fault current before the signal board triggers off a gate signal. Voltage clamping techniques are used to safely turn off the short-circuit current and to prevent overvoltage of the series-connected switches. The selection method of the main devices and the development of the HVS board are described in detail. Experimental results have demonstrated that the HVS board is capable of withstanding a short-circuit current at a rated voltage of 10kV without a di/dt slowing down inductor. The corresponding short-circuit current is restricted to 125 A within 100 ns and can safely turn off within 120 ns.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.96-106
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• 1996

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

• Journal of Power Electronics
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• v.17 no.3
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• pp.716-724
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• 2017

The output voltage of an off-grid inverter is influenced by load current, and the voltage harmonics especially the 5th and 7th are increased with nonlinear loads. In this paper, to attenuate the output voltage harmonics of off-grid inverters with nonlinear loads nearby, a load current feedforward is proposed. It is introduced to a voltage control loop based on the Positive and Negative Sequence Harmonic Regulator (PNSHR) compensation to modify the output impedance at selective frequencies. The parameters of the PNSHR are revised with the output impedance of the off-grid inverter, which minimizes the output impedance of the off-grid inverter. Experimental results verify the proposed method, showing that the output voltage harmonics caused by nonlinear loads can be effectively suppressed.