• Title/Summary/Keyword: number and arithmetic

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An Implementation of Digital Filters Usign the Residue Number System of small Modulus (소 모듈러스들로 구성된 RNS를 사용한 디지털 필터의 실현)

  • Lee, Jeong-Mun;Bae, Jeong-Lee;Choe, Gye-Geun
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.20 no.6
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    • pp.6-10
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    • 1983
  • In this paper, an implementation method for digital filters using the residue arithmetic is proposed. This method can be used for processing digital signals with larger number of bits by applying the idea of the bit-slice algorithm, while previous residue digital filters can process digital signals with only a small number of bits. Furthermore, high-speed residue addition, subtrac-tion, and multiplication using look-up tables make it possible to get more flexible filters. Everything that is mentioned above is proved by implementing a cascade fourth-order Butterworth lowpass digital filter using this method.

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ON AN INVOLUTION ON PARTITIONS WITH CRANK 0

  • Kim, Byungchan
    • East Asian mathematical journal
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    • v.35 no.1
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    • pp.9-15
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    • 2019
  • Kaavya introduce an involution on the set of partitions with crank 0 and studied the number of partitions of n which are invariant under Kaavya's involution. If a partition ${\lambda}$ with crank 0 is invariant under her involution, we say ${\lambda}$ is a self-conjugate partition with crank 0. We prove that the number of such partitions of n is equal to the number of partitions with rank 0 which are invariant under the usual partition conjugation. We also study arithmetic properties of such partitions and their q-theoretic implication.

High-Performance VLSI Architecture Using Distributed Arithmetic for Higher-Order FIR Filters with Complex Coefficients

  • Tsunekawa, Yoshitaka;Nozaki, Takeshi;Tayama, Norio
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.856-859
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    • 2002
  • This paper proposes a high-performance VLSl architecture using distributed arithmetic for higher-order FIR filters with complex coefficients. For the purpose of realizing high sampling rate with small latency in high-order filters, we apply distributed arithmetic[1]. Moreover, in order to decrease drastically the power dissipation, the structure applying not ROM's but optimum function circuits which we have previously proposed, is utilized[2][3]. However, this structure increases in the number of adders as compared to the conventional structure applying ROM's. In order to realize a more effective method for further higher-order filter, we propose newly an implementation applying two methods which have large effects on the unit using the adders. First , we propose an implementation applying SFAs(Serial Full Adders) and SFSs(Serial Full Subtractors). Second, we propose a structure applying proposed 4-2 adders. Finally, it is shown that the proposed architecture is an effective way to realize low power dissipation and small latency while the sampling rate is kept constant for further higher-order filters with complex coefficients.

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Statistical Inference for an Arithmetic Process

  • Francis, Leung Kit-Nam
    • Industrial Engineering and Management Systems
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    • v.1 no.1
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    • pp.87-92
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    • 2002
  • A stochastic process {$A_n$, n = 1, 2, ...} is an arithmetic process (AP) if there exists some real number, d, so that {$A_n$ + (n-1)d, n =1, 2, ...} is a renewal process (RP). AP is a stochastically monotonic process and can be used for modeling a point process, i.e. point events occurring in a haphazard way in time (or space), especially with a trend. For example, the vents may be failures arising from a deteriorating machine; and such a series of failures id distributed haphazardly along a time continuum. In this paper, we discuss estimation procedures for an AP, similar to those for a geometric process (GP) proposed by Lam (1992). Two statistics are suggested for testing whether a given process is an AP. If this is so, we can estimate the parameters d, ${\mu}_{A1}$ and ${\sigma}^{2}_{A1}$ of the AP based on the techniques of simple linear regression, where ${\mu}_{A1}$ and ${\sigma}^2_{A1}$ are the mean and variance of the first random variable $A_1$ respectively. In this paper, the procedures are, for the most part, discussed in reliability terminology. Of course, the methods are valid in any area of application, in which case they should be interpreted accordingly.

Design and Implementation of Arbitrary Precision Class for Public Key Crypto API based on Java Card (자바카드 기반 공개키 암호 API를 위한 임의의 정수 클래스 설계 및 구현)

  • Kim, Sung-Jun;Lee, Hei-Gyu;Cho, Han-Jin;Lee, Jae-Kwang
    • The KIPS Transactions:PartC
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    • v.9C no.2
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    • pp.163-172
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    • 2002
  • Java Card API porvide benifit for development program based on smart card using limmited resource. This APIs does not support arithmetic operations such as modular arithmetic, greatest common divisor calculation, and generation and certification of prime number, which is necessary arithmetic in PKI algorithm implementation. In this paper, we implement class BigInteger acted in the Java Card platform because that Java Card APIs does not support class BigInteger necessary in implementation of PKI algorithm.

Efficient programmable power-of-two scaler for the three-moduli set {2n+p, 2n - 1, 2n+1 - 1}

  • Taheri, MohammadReza;Navi, Keivan;Molahosseini, Amir Sabbagh
    • ETRI Journal
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    • v.42 no.4
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    • pp.596-607
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    • 2020
  • Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)-based DSPs, scaling represents a performance bottleneck based on the complexity of intermodulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well-known moduli sets {2n - 1, 2n, 2n + 1} and {2n, 2n - 1, 2n+1 - 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic-friendly moduli set {2n+p, 2n - 1, 2n+1 - 1}. The proposed algorithm yields high speed and energy-efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed-radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

Fast Sequential Optimal Normal Bases Multipliers over Finite Fields (유한체위에서의 고속 최적정규기저 직렬 연산기)

  • Kim, Yong-Tae
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.8
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    • pp.1207-1212
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    • 2013
  • Arithmetic operations over finite fields are widely used in coding theory and cryptography. In both of these applications, there is a need to design low complexity finite field arithmetic units. The complexity of such a unit largely depends on how the field elements are represented. Among them, representation of elements using a optimal normal basis is quite attractive. Using an algorithm minimizing the number of 1's of multiplication matrix, in this paper, we propose a multiplier which is time and area efficient over finite fields with optimal normal basis.

ON SOLVING FUZZY EQUATION

  • Hong, Dug-Hun
    • Journal of applied mathematics & informatics
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    • v.8 no.1
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    • pp.213-223
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    • 2001
  • The use of fuzzy number over interval of confidence instead of possibilitic consideration for solving fuzzy equation is proposed. This approach of solving fuzzy equation by interval arithmetic and ${\alpha}$-cuts has a considerable advantage. Through theoretical analysis, an illustrative example and computational results, we show that the proposed approach is more general and straight-forword.

Words for Numbers and Transcoding Processes Reflected by ERPs during Mental Arithmetic (수 연산과정에서 ERP로 확인된 숫자어휘와 부호변환 과정)

  • Kim, Choong-Myung;Kim, Dong-Hwee
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.2
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    • pp.689-695
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    • 2010
  • The effect of the code conversion process of Korean script (Hangul), also known as words for numbers, was investigated using event-related potentials (ERPs) during mental arithmetic operations. Study subjects were asked to determine whether the arithmetic results of a given target stimuli were correctly matched. Visual inspection and statistics of mean ERPs showed stimulus type-dependent processing rather than task-dependent processing. Results of addition and multiplication tasks revealed that the overall temporal profiles of the Arabic numerals were similar to the Hangul words for numbers. The only exception to this observation was a delayed positive-slope peak occurring around 300 ms, which was likely related to the encoding process of Hangul words for numbers to Arabic-digits, defined as a 'transcoding-related potential.' Source analysis confirmed that the topography of different waveforms for the two conditions was attributed to a single dipole located in the left temporo-parietal area; this area is known to be involved in Hangul words for number processing. These results suggest that the initial processing for encoding words for numbers was followed by arithmetic operations without direct access of internal number representation. Korea Academia-Industrial cooperation Society. The Korea Academia-Industrial cooperation Society. The Korea Academia-Industrial cooperation Society. The Korea Academia-Industrial cooperation Society.