• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.188-189
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• 2002

One of the current goals in memory device developments is to realize a nonvolatile memory, i.e., the stored information maintains even when the power is turned off. The representative candidates for nonvolatile memories are magnetic random access memory (MRAM) and ferroelectric random access memory (FRAM). In order to achieve a high density memory in MRAM device, the external magnetic field should be localized in a tiny cell to control the direction of spontaneous magnetization. (omitted)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.112-115
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• 2003

There is a growing need for a nonvolatile memory technology with faster speed than existing nonvolatile memories. $T_c$(crystallization temperature) is confirmed by measuring the conductivity with the varying temperature. The sample is heated on the hotplate and slow down to the room-temperature. We prepared Te based alloy bulk. The materials can be used for nonvolatile random access memory.

• Journal of IKEEE
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• v.27 no.4
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• pp.386-390
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• 2023

In this study, we examined the quasi-nonvolatile memory characteristics of silicon nanosheet (SiNS) feedback field-effect transistors (FBFETs) fabricated using a complementary metal-oxide-semiconductor process. The SiNS channel layers fabricated by photoresist overexposure method had a width of approximately 180 nm and a height of 70 nm. The SiNS FBFETs operated in a positive feedback loop mechanism and exhibited an extremely low subthreshold swing of 1.1 mV/dec and a high ON/OFF current ratio of 2.4×10⁷. Moreover, SiNS FBFETs represented long retention time of 50 seconds, indicating the quasi-nonvolatile memory characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.282.1-282.1
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• 2016

The remarkable physical properties of two-dimensional (2D) semiconducting materials such as molybdenum disulfide ($MoS_2$) and tungsten disulfide ($WS_2$) etc. have attracted considerable attentions for future high-performance electronic and optoelectronic devices. The ongoing studies of $MoS_2$ based nonvolatile memories have been demonstrated by worldwide researchers. The opening hysteresis in transfer characteristics have been revealed by different charge confining layer, for instance, few-layer graphene, $MoS_2$, metallic nanocrystal, hafnium oxide, and guanine. However, limited works built their nonvolatile memories using entirely of assembled 2D crystals. This is important in aspect view of large-scale manufacture and vertical integration for future memory device engineering. We report $WS_2$ based nonvolatile memories utilizing functional van der Waals heterostructure in which multi-layered graphene is encapsulated between $SiO_2$ and hexagonal boron nitride (hBN). We experimentally observed that, large memory window (20 V) allows to reveal high on-/off-state ratio (>$10^3$). Moreover, the devices manifest perfect retention of 13% charge loss after 10 years due to large graphene/hBN barrier height. Interestingly, the performance of our memories is drastically better than ever published work related to $MoS_2$ and black phosphorus flash memory technology.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.727-736
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• 1995

This paper examines the characteristics and physical properties of the scaled MONOS nonvolatile memory device for low programming voltage EEPROM. The capacitor-type MONOS memory devices with the nitride thicknesses ranging from 41.angs. to 600.angs. have been fabricated. As a result, the 5V-programmable MONOS device has been obtained with a 20ms programming time by scaling the nitride thickness to 57.angs. with a tunneling oxide thickness of 19.angs. and a blocking oxide thickness of 20.angs.. Measurement results of the quasi-static C-V curves indicate, after 10$\^$6/ write/erase cycles, that the devices are degraded due to the increase of the silicon-tunneling oxide interface traps. The 10-year retention is impossible for the device with a nitride less than 129.angs.. However, the MONOS memory device with 10-year retentivity has been obtained by increasing the blocking oxide thickness to 47.angs.. Also, the memory traps such as the nitride bulk trap and the blocking oxide-nitride interface trap have been investigated by measuring the maximum flatband voltage shift and analyzing through the best fitting method.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.13-17
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• 1996

Superthin ONO ( oxide -nitride - oxide ) structures were fabricated for the MONOS nonvolatile memory device with a 20$\AA$ tunneling oxide, 40$\AA$ nitride and 40$\AA$ blocking oxide. The compositions of each layer in a superthin ONO structure were investigated. Also, the characteristics of trap related to the memory quality were examined.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.28.2-28.2
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• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.