• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.7-12
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• 2016

DRAM is commonly used as a smartphone memory medium, but extending its capacity is challenging due to DRAM's large battery consumption and density limit. Meanwhile, smartphone applications such as social network services need increasingly large memory, resulting in long latency due to additional storage accesses. To alleviate this situation, we adopt emerging nonvolatile memory (NVRAM) as smartphone's buffer cache and propose an efficient management scheme. The proposed scheme stores all dirty data in NVRAM, thereby reducing the number of storage accesses. Moreover, it separately exploits read and write histories of data accesses, leading to more efficient management of volatile and nonvolatile buffer caches, respectively. Trace-driven simulations show that the proposed scheme improves I/O performances significantly.

• International Journal of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.133-133
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• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• Transactions on Electrical and Electronic Materials
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• v.5 no.6
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• pp.227-232
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• 2004

We investigated a nonvolatile nanomemory element based on boron nitride nanopeapods using molecular dynamics simulations. The studied system was composed of two boron-nitride nanotubes filled Cu electrodes and fully ionized endo-fullerenes. The two boron-nitride nanotubes were placed face to face and the endo-fullerenes came and went between the two boron-nitride nanotubes under alternatively applied force fields. Since the endo-fullerenes encapsulated in the boron-nitride nanotubes hardly escape from the boron-nitride nanotubes, the studied system can be considered to be a nonvolatile memory device. The minimum potential energies of the memory element were found near the fullerenes attached copper electrodes and the activation energy barrier was $3{\cdot}579 eV$. Several switching processes were investigated for external force fields using molecular dynamics simulations. The bit flips were achieved from the external force field of above $3.579 eV/{\AA}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.17-21
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• 2009

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• ETRI Journal
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• v.35 no.4
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• pp.734-737
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• 2013

Nonvolatile ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) memory based on an organic thin-film transistor with inkjet-printed dodecyl-substituted thienylenevinylene-thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of -12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 $cm^2/Vs$, $10^5$, and $10^{-10}$ A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.231-232
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• 2016

We have fabricated the nc-Si, IGZO based nonvolatile memory TFTs using mobile protons, which can be generated by simple hydrogen insertion process via H-NB treatment at room temperature. The TFT devices above exhibited reproducible hysteresis behavior, stable ON/OFF switching, and non-volatile memory characteristics. Also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and our modified H-NB CVD. The room temperature proton-insertion process can reveal flexible inorganic based all-in-one display panel including driving circuit and memory circuit.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.46-49
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• 1994

In this paper we investigate the characteristics of switching and memory traps in sealed MONOS nonvolatile memory devices with different nitride thicknesses. We have demonttrated flatband voltage shift of 1V with 5V programming voltage. By fitting the experimental observations with theoretical calculations, trap density and capture cross section of memory trap at the nitride-blocking oxide interface are estimated to be 1.0${\times}$10$\^$13/ cm$\^$-2/ and 8.0${\times}$10$\^$14/ cm$\^$-2/

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.904-906
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• 2009

Organic field-effect transistor (OFET) memory is an emerging device for its potential to realize light-weight, low cost flexible charge storage media. Here we report on a solution-processed poly[9,9-dioctylfluorenyl-2,7-diyl]-co-(bithiophene)] (F8T2) nano floating-gate memory (NFGM) with top-gate/bottom-contact device configuration. A reversible shift in the threshold voltage ($V_{Th}$) and the reliable memory characteristics were achieved by incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative electrons at the interface between polystyrene and cross-linked poly(4-vinylphenol).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.10a
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• pp.14-17
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• 1988

Degradation effects observed in nonvolatile MNOS memory devices with in increasing W/E (Write/Erase) cycling were investigated using n-type MNOS capacitors. The results showed that the density of Si-SiO$_2$ interface states and the conductivity of nitride were increased with W/E cycles, therefore the memory retention characteristics of the MNOS memory devices were degraded. Also, annealing of the degraded devices restored the original Si-SiO$_2$ interface states density, but failed to restore the original nitride conductivity. Based on these experimental results, we found that the degradation of memory retention characteristic was affected by the nitride conductivity rather than by Si-SiO$_2$ interface states.