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http://dx.doi.org/10.4313/JKEM.2009.22.1.017

Study of Nonvolatile Memory Device with SiO2/Si3N4 Stacked Tunneling Oxide  

Cho, Won-Ju (광운대학교 전자재료공학과)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.22, no.1, 2009 , pp. 17-21 More about this Journal
Abstract
The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated for nonvolatile memory device applications. The band structure of band-gap engineered tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with the conventional tunneling $SiO_2$ barrier. The band-gap engineered tunneling barriers composed of thin $SiO_2$ and $Si_3N_4$ layers showed a lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.
Keywords
Nonvolatile memory; $SiO_2$/$Si_3N_4$; Band gap engineered tunnel barrier;
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Times Cited By KSCI : 1  (Citation Analysis)
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