• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.8
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• pp.596-600
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• 1998

A method for the nondestructive read-out of the memory in ferroelectric thin films is demonstrated using the detection second harmonic currents introduced in the ferrolelectric capacitor as a response to an ac signal. The sign and phase of the second harmonic current depends on the polarized state +$P_r or -P_r$, The studied ferroelectric PZT thin film is found to have desirable features for the use as a memory element. This method and material seems as a promising approach for the nonvolatile memory storage.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.72-76
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• 2020

The author demonstrated organic ferroelectric thin-film transistors with ferroelectric materials of P(VDF-TrFE) and an amorphous oxide semiconducting In-Ga-Zn-O channel on the silicon substrates. The organic ferroelectric layers were deposited on an oxide semiconductor layer by Langmuir-Blodgett method and then annealed at 128℃ for 30min. The carrier mobility and current on/off ratio of the memory transistors showed 9 ㎠V^-1s^-1 and 6 orders of magnitude, respectively. We can conclude from the obtained results that proposed memory transistors were quite suitable to realize flexible and werable electronic applications.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.82-82
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• 1999

Ferroelectric materials are characterized by the existence of a spontaneous remnant polarization that can be switched between two stable states by an applied field. This phenomenon is known as ferroelectricity. The ferroelectricity can be utilized for nonvolatile memory application. Up to now 256K FRAM was successfully fabricated and sold in the memory market. This paper will briefly review the current statue of ferroelectric random access memory (FRAM) focusing on recent developments. In addition, the future prospects of FRAM will be addressed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.415-416
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• 2009

The tunnel barrier engineered charge trap flash (TBE-CTF) non-volatile memory using CRESTED tunneling barrier was fabricated by stacking thin $Si_3N_4$ and $SiO_2$ dielectric layers. Moreover, high-k based $HfO_2$ charge trap layer and $Al_2O_3$ blocking layer were used for further improvement of the NVM (non-volatile memory) performances. The programming/erasing speed, endurance and data retention of TBE-CTF memory was evaluated.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.799-803
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• 2018

We demonstrated memory thin-film transistors (MTFTs) with organic ferroelectric polymer poly(vinylidene fluoride-co-trifluoroethylene) and an amorphous oxide semiconducting indium gallium zinc oxide channel on the elastomeric substrate. The dielectric constant for the P(VDF-TrFE) thin film prepared on the elastomeric substrate was calculated to be 10 at a high frequency of 1 MHz. The voltage-dependent capacitance variations showed typical butterfly-shaped hysteresis behaviors owing to the polarization reversal in the film. The carrier mobility and memory on/off ratio of the MTFTs showed $15cm^2V^{-1}s^{-1}$ and $10^6$, respectively. This result indicates that the P(VDF-TrFE) film prepared on the elastomeric substrate exhibits ferroelectric natures. The fabricated MTFTs exhibited sufficiently encouraging device characteristics even on the elastomeric substrate to realize mechanically stretchable nonvolatile memory devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2007.02a
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• pp.149-149
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• 2007

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.255-255
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• 2009

In this work, nonvolatile nano-floating gate memory devices were fabricated with ZnO films and Al nanoparticles using the sputtering method on a glass substrate. Al nanoparticles acted as floating gate nodes in the devices. The fabricated device exhibits a threshold voltage shift of 1.7 V.