• Nuclear Engineering and Technology
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• v.39 no.6
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• pp.717-724
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• 2007

A measurement-based time-domain noise simulation of radiation detector-preamplifier (front-end) noise in nuclear spectroscopy is described. The time-domain noise simulation was performed by generating "noise random numbers" using Monte Carlo's inverse method. The probability of unpredictable noise was derived from the empirical cumulative distribution function via the sampled noise, which was measured from a preamplifier output. Results of the simulated noise were investigated as functions of time, frequency, and statistical domains. Noise behavior was evaluated using the signal wave-shaping function, and was compared with the actual noise. Similarities between the response characteristics of the simulated and the actual preamplifier output noises were found. The simulated noise and the computed nuclear pulse signal were also combined to generate a simulated preamplifier output signal. Such simulated output signals could be used in nuclear spectroscopy to determine energy resolution degradation from front-end noise effect.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Journal of Ocean Engineering and Technology
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• v.6 no.2
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• pp.41-45
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• 1992

In this paper an application technique of moment equation method to solution of nonlinear rolling equation of motion of ships is investigated. The exciting moment in the equation of rolling motion of ships is described as non-white noise. This non-white exciting moment is generated through use of a shaping filter. These coupled equations are used to generate moment equations. The nonstationary responses of the nonlinear system are obtained. The results are compared with those of a linear system.

• Journal of IKEEE
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• v.17 no.4
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• pp.511-516
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• 2013

This paper presents a SDM using the FDPA technique. The FDPA technique is the added feedback path which is the delayed path of DAC output. The designed SDM increases the SNR by adding the delayed digital feedback path. The proposed SDM is easily implemented by eliminating the analog feedback path. Through the MATLAB modeling, the optimized coefficients are obtained to design the SDM. The designed SDM has a power consumption of $220{\mu}W$ and SNR(signal to noise ratio) of 81dB at the signal-bandwidth of 20KHz and sampling frequency of 2.56MHz. The SDM is designed using the $0.18{\mu}m$ standard CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.276-281
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• 2010

A 2.5 V feed-forward second-order deltasigma modulator for audio application is presented. A 9-level quantizer with a tree-structured dynamic element matching (DEM) was employed to improve the linearity by shaping the distortion resulted from the capacitor mismatch of the feedback digital-toanalog converter (DAC). A chopper stabilization technique (CHS) is used to reduce the flicker noise in the first integrator. The prototype delta-sigma analogto-digital converter (ADC) implemented in a 65 nm 1P8M CMOS process occupies 0.747 $mm^2$ and achieves 109.1 dB dynamic range (DR), 85.4 dB signal-to-noise ratio (SNR) in a 24 kHz audio signal bandwidth, while consuming 14.75 mW from a 2.5 V supply.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.3
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• pp.17-26
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• 2005

The random pulse width modulation(RPWM) in inverter-fed induction motor drive is presented. This paper describes a RPWM method based on space vector PWM strategy for shaping the switching noise spectrum in such a way it can merge with the natural system noise. To verify the validity of the proposed RPWM scheme, the experiment based on the DSP56F803 microprocessor was executed finally, the simulation and experimental results will be given to demonstrate the effectiveness of the unposed RPWM scheme.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.4
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• pp.8-15
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• 2000

In this paper, we realize the active PFC(Power Factor Correction) system of BF(Boost Forward) converter with PWM-PFM(Pulse Width Modulation-Pulse Frequency Modulation) control technique to control DC output voltage, to remove the noise like harmonics at output voltage, and to control the input current with sinusoidal wave synchronized by the source voltage.To achieve the desired load voltage and improved PFC, we first implement current shaping control at the inverting stage and make the converted output DC voltage with forward converter. After making the ratio of output voltage to current as 50V/1A and the duty ratio greater than 0.5. When input voltage is 30V and boost inductance is 1.1mH. we control the voltage changing rate according to the variation of load resistance using a PWM-PFM control technique. And finally we prove experimentally, we attenuated its harmonics and improved PF up to 0.96 using the current shaping technique.

• Journal of IKEEE
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• v.18 no.2
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• pp.192-197
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• 2014

In this paper, $3^{rd}$ SDM with FDPA(Feedback Delay Pass Addition) technique to improve the input range is proposed. Conventional architecture with $3^{rd}$ transfer function is just made as adding a digital delay path in $2^{nd}$ SDM architecture. But the input range is very small because feedback path into the first integrator is increased. But, proposed architecture change feedback path into the first integrator to the second integrator, so input range could be improved about 9dB. The $3^{rd}$ SC SDM with only one operational amplifier was implemented using double-sampling technique. Simulation results for the proposed SDM designed in $0.18{\mu}m$ CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and audible sampling frequency 2.8224MHz show SNR(Signal to Noise Ratio) of 83.8dB, the power consumption of $700{\mu}W$ and Dynamic Range of 82.8dB.

• Journal of KSNVE
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• v.6 no.6
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• pp.763-770
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• 1996

This paper proposes a method to determine the initial shape and size of the suspension beam of an optical pickup actuator subjected to specified dynamic characteristics. For the analysis, a simplified model consisting of a concentrated mass, rotational springs and beams is developed. Based on this model, the key dimensionless design parameters are introduced, which govern low-frequency vibration characteristics i. e., the resonant frequencies in the tracking and focusing directions. A systematic procedure for sizing and shaping the actuator suspension beams is described and applied to a sample case. The effectiveness of the present technique is verified through the comparison of the present and the finite element results.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.19-26
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• 2011

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.