• 제목/요약/키워드: noise power mismatch

검색결과 34건 처리시간 0.027초

Scaled-Energy Based Spectrum Sensing for Multiple Antennas Cognitive Radio

  • Azage, Michael Dejene;Lee, Chaewoo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제12권11호
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    • pp.5382-5403
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    • 2018
  • In this paper, for a spectrum sensing purpose, we heuristically established a test statistic (TS) from a sample covariance matrix (SCM) for multiple antennas based cognitive radio. The TS is formulated as a scaled-energy which is calculated as a sum of scaled diagonal entries of a SCM; each of the diagonal entries of a SCM scaled by corresponding row's Euclidean norm. On the top of that, by combining theoretical results together with simulation observations, we have approximated a decision threshold of the TS which does not need prior knowledge of noise power and primary user signal. Furthermore, simulation results - which are obtained in a fading environment and in a spatially correlating channel model - show that the proposed method stands effect of noise power mismatch (non-uniform noise power) and has significant performance improvement compared with state-of-the-art test statistics.

Assessment of Gradient-based Digital Speckle Correlation Measurement Errors

  • Jian, Zhao;Dong, Zhao;Zhe, Zhang
    • Journal of the Optical Society of Korea
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    • 제16권4호
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    • pp.372-380
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    • 2012
  • The optical method Digital Speckle Correlation Measurement (DSCM) has been extensively applied due its capability to measure the entire displacement field over a body surface. A formula of displacement measurement errors by the gradient-based DSCM method was derived. The errors were found to explicitly relate to the image grayscale errors consisting of sub-pixel interpolation algorithm errors, image noise, and subset deformation mismatch at each point of the subset. A power-law dependence of the standard deviation of displacement measurement errors on the subset size was established when the subset deformation was rigid body translation and random image noise was dominant and it was confirmed by both the numerical and experimental results. In a gradient-based algorithm the basic assumption is rigid body translation of the interrogated subsets, however, this is in contradiction to the real circumstances where strains exist. Numerical and experimental results also indicated that, subset shape function mismatch was dominant when the order of the assumed subset shape function was lower than that of the actual subset deformation field and the power-law dependence clearly broke down. The power-law relationship further leads to a simple criterion for choosing a suitable subset size, image quality, sub-pixel algorithm, and subset shape function for DSCM.

잡음지수분석기의 새로운 교정방법과 잡음상관행렬 측정 (Novel Calibration Method of Noise Figure Analyzer and Measurement of Noise Correlation Matrix)

  • 이동현;염경환
    • 한국전자파학회논문지
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    • 제29권7호
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    • pp.491-499
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    • 2018
  • 잡음지수분석기의 일반적인 교정방법은 잡음전원을 이용하는 방법이다. 이 방법은 교정 시 잡음전원과 잡음지수분석기의 부정합을 고려하지 않기 때문에 측정결과에서 심각한 불규칙 리플을 동반한다. 본 논문에서는 잡음전원과 잡음지수분석기의 부정합을 모두 고려한 새로운 잡음지수분석기의 교정 및 이를 이용한 새로운 잡음상관행렬 측정방법을 제안한다. 제안하는 방법은 uncorrected 잡음전력을 이용, 교정하지 않은 잡음지수분석기의 이득과 잡음상관행렬을 결정하였다. 그리고 결정된 이득과 잡음상관행렬을 이용, DUT에 대한 잡음상관행렬 측정결과에서 잡음지수분석기의 영향을 교정하였다. 제안된 방법을 통해, 측정된 DUT의 잡음파라미터는 상대적인 잡음비를 이용한 측정 결과와 같은 정도의 불규칙 리플을 보였다.

Gain and Phase Mismatch Calibration Technique in Image-Reject RF Receiver

  • Lee, Mi-Young;Yoo, Chang-Sik
    • Journal of electromagnetic engineering and science
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    • 제10권1호
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    • pp.25-27
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    • 2010
  • This paper presents a gain and phase mismatch calibration technique for an image-reject RF receiver. The gain mismatch is calibrated by directly measuring the output signal amplitudes of two signal paths. The phase mismatch is calibrated by measuring the output amplitude of the final IF output at the image band. The calibration of the gain and phase mismatch is performed at power-up, and the normal operation of the RF receiver does not interfere with the mismatch calibration circuit. To verify the proposed technique, a 2.4-GHz Weaver image-reject receiver with the gain and phase mismatch calibration circuit is implemented in a 0.18-${\mu}m$ CMOS technology. The overall receiver achieves a voltage gain of 45 dB and a noise figure of 4.8 dB. The image rejection ratio(IRR) is improved from 31 dB to 59.76 dB even with 1 dB and $5^{\circ}$ mismatch in gain and phase, respectively.

Spectral Subtraction Using Spectral Harmonics for Robust Speech Recognition in Car Environments

  • Beh, Jounghoon;Ko, Hanseok
    • The Journal of the Acoustical Society of Korea
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    • 제22권2E호
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    • pp.62-68
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    • 2003
  • This paper addresses a novel noise-compensation scheme to solve the mismatch problem between training and testing condition for the automatic speech recognition (ASR) system, specifically in car environment. The conventional spectral subtraction schemes rely on the signal-to-noise ratio (SNR) such that attenuation is imposed on that part of the spectrum that appears to have low SNR, and accentuation is made on that part of high SNR. However, these schemes are based on the postulation that the power spectrum of noise is in general at the lower level in magnitude than that of speech. Therefore, while such postulation is adequate for high SNR environment, it is grossly inadequate for low SNR scenarios such as that of car environment. This paper proposes an efficient spectral subtraction scheme focused specifically to low SNR noisy environment by extracting harmonics distinctively in speech spectrum. Representative experiments confirm the superior performance of the proposed method over conventional methods. The experiments are conducted using car noise-corrupted utterances of Aurora2 corpus.

Performance Analysis of Array Processing Techniques for GNSS Receivers under Array Uncertainties

  • Lee, Sangwoo;Heo, Moon-Beom;Sin, Cheonsig;Kim, Sunwoo
    • Journal of Positioning, Navigation, and Timing
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    • 제6권2호
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    • pp.43-51
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    • 2017
  • In this study, the effect of the steering vector model mismatch due to array uncertainties on the performance of array processing was analyzed through simulation, along with the alleviation of the model mismatch effect depending on array calibration. To increase the reliability of the simulation results, the actual steering vector of the array antenna obtained by electromagnetic simulation was used along with the Jahn's channel model, which is an experimental channel model. Based on the analysis of the power spectrum for each direction, beam pattern, and the signal-to-interference-plus-noise ratio of the beamformer output, the performance deterioration of array processing due to array uncertainties was examined, and the performance improvement of array processing through array calibration was also examined.

마이크로스트립 선로에서 Sn-O 박막의 전도노이즈 흡수 특성 (Conduction Noise Absorption by Sn-O Thin Films on Microstrip Lines)

  • 김성수
    • 대한금속재료학회지
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    • 제49권4호
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    • pp.329-333
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    • 2011
  • To develop wide-band noise absorbers with a special design for low-frequency performance, this study proposes a tin oxide (Sn-O) thin films as the noise absorbing materials in a microstrip line. Sn-O thin films were deposited on polyimide film substrates by reactive sputtering of the Sn target under flowing $O_{2}$ gas, exhibiting a wide variation of surface resistance (in the range of $10^{0}-10^{5}{\Omega}$) depending on the oxygen partial pressure during deposition. The microstrip line with characteristic impedance of $50\Omega$ was used for the measurement of noise absorption by the Sn-O films. The reflection parameter $(S_{11})$ increased with a decrease of surface resistance due to an impedance mismatch at the boundary between the film and the microstrip line. Meanwhile, the transmission parameter $(S_{21})$ diminished with a decrease of surface resistance resulting from an Ohmic loss of the Sn-O films. The maximum noise absorption predicted at an optimum surface resistance of the Sn-O films was about $150{\Omega}$. For this film, greater power absorption is predicted in the lower frequency region (about 70% at 1 GHz) than in conventional magnetic sheets of high magnetic loss, indicating that Ohmic loss is the predominant loss parameter for the conduction noise absorption in the low frequency band.

A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

  • Yamauchi, Hiroyuki
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권2호
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    • pp.118-129
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    • 2010
  • A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

빠른 스위칭 시간과 저 위상잡음 특성을 가지는 PHS용 주파수 합성기의 설계 (A design of fast switching time, low phase noise PHS frequency synthesizer)

  • 정성규;정지훈;부영건;김진경;장석환;이강윤
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.499-500
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    • 2006
  • This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

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Rail-to-Rail의 입력 신호 범위를 가지는 12-bit 1MS/s 축차비교형 아날로그-디지털 변환기 (A 12-bit 1MS/s SAR ADC with Rail-to-Rail Input Range)

  • 김두연;정재진;임신일;김석기
    • 전기학회논문지
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    • 제59권2호
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    • pp.355-358
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    • 2010
  • As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.