• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1737-1743
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• 2006

OCR(On channel repeater) provides the high frequency reuse efficiency for allocating frequency bands to repeaters because the frequency of input and output signals of OCRs is the same. However the oscillation probability of OCRs is high due to the same input and output frequency. In order to prevent a repeater from oscillating, we must keep the antenna isolation higher than the gain of the repeater with a some margin. In this paper we simulated the effects of the amplitude, phase and time delay of feedback signals (m the characteristics of non-regeneration OCR. Simulation results show that the highest probability of oscillation is occurred when the gain of a repeater is the same value of the isolation. From the simulation results, we know that the phase of feedback signals can be adjusted to reduce the possibility of oscillation if a non-regeneration repeater has a narrow operation bandwidth or a signal bandwidth is narrow. As the time delay increases, the probability of oscillation and the fluctuation of gain over a certain frequency band increase also. The effects of the amplitude and phase of feedback signals on S/N of 8-VSB signal for generation and non-generation repeater were tested. The measured results show that the set-top can receive 8-VSB signal when the received signal power is $17{\sim}18dB$ higher than the noise power. When the isolation is almost same as the gain of the repeater, then the set-top can not receive 8-VSB signals due to the oscillation of the repeater. And the phase of feedback signals affects S/N at the output of the repeater when the isolation is $11.75{\sim}13.75dB$ larger than the gain of the repeater. In this case the set-top can not receive 8-VSB signal of at $48^{\circ}\;and\;347^{\circ}$ of the phase of feedback signals. However the phase of feedback signals can not affect the S/N of 8-VSB signals of the generation repeater because of the demodulation and modulation process of the generation repenter. The set-top can not receive 8-VSB signals when the amplitude of feedback signals is $12.6{\sim}13.6dB$ larger than the wanted signal power at the input port of the repeater. It's because that the amplitude of feedback signals saturates the front end of the repeater.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.