• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권2호
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• pp.87-92
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• 2001

This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is $2{\times}2$, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2${\mu}m$ double poly CMOS parameters of MOSIS fabrication process.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1994년도 FIFTH WESTERN PACIFIC REGIONAL ACOUSTICS CONFERENCE SEOUL KOREA
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• pp.830-835
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• 1994

In this paper, a new method of statistically evaluating an output response probability distribution of a memory type non-linear system is practically derived based on a zero-memory type non-linear equivalent system. That is, first, the objective system is approximately and functionally separated into two functional parts, i.e., a zero-memory type non-linear part and a memory type linear part according to the well-known Wiener's idea. A whole mathematical frame of the output probability distribution is evaluated in an approximate but generalized form, based on the equivalent zero-memory type non-linear part. The memory effects between the input and the output of the system are reflected in the statistical parameters and the expansion coefficients.

• Journal of Communications and Networks
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• 제17권3호
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• pp.286-295
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• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.

• 한국정보통신학회논문지
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• 제20권12호
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• pp.2282-2288
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• 2016

보안키 생성기법으로 하드웨어 또는 소프트웨어 관련 생성기법들이 다양하게 제안되고 있다. 본 연구는 기존의 보안키 생성기법들을 분석하여, NAND 플래시 메모리의 Bad Block 정보를 이용하는 새로운 보안키인 NBSK(NAND Bad block based Secure Key)을 설계하고 이를 이용한 암호화기법을 제안한다. NAND 플래시 메모리에 존재하는 Bad Block은 생산중에 발생하기도 하고 사용 도중에 발생하기도 한다. 생산중 발생하는 초기 Bad Block 정보는 변하지 않으며, 사용도중 발생하는 Bad Block 정보는 주기적으로 변할 수 있다는 특성을 가지고 있다. 따라서 본 연구는 NAND 플래시 메모리 생산중에 발생하는 초기의 Bad Block 정보의 물리주소를 이용하여 보안키로 활용할 수 있도록 암호화키를 설계하고 이를 이용한 암호화 기법을 제안한다. 제안 기법을 이용하면 보안키의 생성과 분배의 단순성과 보안키의 인증성과 기밀성 등의 일반적인 보안 특성을 만족할 수 있다.

• Journal of Computing Science and Engineering
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• 제8권3호
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• pp.157-172
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• 2014

Contemporary embedded systems often use NAND flash memory instead of hard disks as their swap space of virtual memory. Since the read/write characteristics of NAND flash memory are very different from those of hard disks, an efficient page replacement algorithm is needed for this environment. Our analysis shows that temporal locality is dominant in virtual memory references but that is not the case for write references, when the read and write references are monitored separately. Based on this observation, we present a new page replacement algorithm that uses different strategies for read and write operations in predicting the re-reference likelihood of pages. For read operations, only temporal locality is used; but for write operations, both write frequency and temporal locality are used. The algorithm logically partitions the memory space into read and write areas to keep track of their reference patterns precisely, and then dynamically adjusts their size based on their reference patterns and I/O costs. Without requiring any external parameter to tune, the proposed algorithm outperforms CLOCK, CAR, and CFLRU by 20%-66%. It also supports optimized implementations for virtual memory systems.

• 한국멀티미디어학회논문지
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• 제14권1호
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• pp.94-102
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• 2011

JPEG2000 시스템에서 요구하는 메모리의 크기와 대역폭을 감소시키기 위하여 본 논문은 약간의 화질 손실이 있는 새로운 임베디드 압축(Embedded Compression) 알고리즘을 제안한다. 또한, 메모리 내의 압축된 데이터에 임의 접근성(Random Accessibility)과 짧은 지연 시간(Latency)을 보장하기 위해서 매우 단순하면서도 효율적인 하다마드(Hadamard) 변환 기반의 부호화 방식을 제안한다. JPEG2000 표준안의 알고리즘에 변경을 주지 않고, 제안한 EC 알고리즘을 통해 LL 임시 메모리의 크기와 코드블록 메모리의 크기를 약 2 배로 줄이며, 약 52~73%의 메모리 대역폭을 감소시킬 수 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1426-1427
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• 2006

Chalcogenide based phase-change memory has a high capability and potential for the next generation nonvolatile memory device. Fast writing speed, low writing voltage, high sensing margin, low power consume and long cycle of read/write repeatability are also good advantages of nonvolatile phase-change memory. We have been investigated the new material for the phase-change memory. Its composition is consists of chalcogenide $Ge_{1}Se_{1}Te_2$ material. We made this new material to solve problems of conventional phase-change memory which has disadvantage of high power consume and high writing voltage. In the present work, we are manufactured $Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}$ and $Ge_{2}Sb_{2}Te_{5}/Ge_{1}Se_{1}Te_{2}/Ge_{2}Sb_{2}Te_{5}$ sandwich triple layer structure devices are manufactured to investigate its electrical properties. Through the present work, we are willing to ensure a potential of substitutional method to overcome a crystallization problem on PRAM device.

• Molecules and Cells
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• 제23권3호
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• pp.259-271
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• 2007

Investigation of molecular and cellular mechanisms of synaptic plasticity is the major focus of many neuroscientists. There are two major reasons for searching new genes and molecules contributing to central plasticity: first, it provides basic neural mechanism for learning and memory, a key function of the brain; second, it provides new targets for treating brain-related disease. Long-term potentiation (LTP), mostly intensely studies in the hippocampus and amygdala, is proposed to be a cellular model for learning and memory. Although it remains difficult to understand the roles of LTP in hippocampus-related memory, a role of LTP in fear, a simplified form of memory, has been established. Here, I will review recent cellular studies of LTP in the anterior cingulate cortex (ACC) and then compare studies in vivo and in vitro LTP by genetic/pharmacological approaches. I propose that ACC LTP may serve as a cellular model for studying central sensitization that related to chronic pain, as well as pain-related cognitive emotional disorders. Understanding signaling pathways related to ACC LTP may help us to identify novel drug target for various mental disorders.

• 전자통신동향분석
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• 제35권3호
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.