• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.223-231
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• 2015

As smartphones support a variety of applications and their memory demand keeps increasing, the design of an efficient memory management policy is becoming increasingly important. Meanwhile, as nonvolatile memory (NVM) technologies such as PCM and STT-MRAM have emerged as new memory media of smartphones, characterizing memory references for NVM-based smartphone memory systems is needed. For the deep understanding of memory access features in smartphones, this paper performs comprehensive analysis of memory references for various smartphone applications. We first analyze the temporal locality and frequency of memory reference behaviors to quantify the effects of the two properties with respect to the re-reference likelihood of pages. We also analyze the skewed popularity of memory references and model it as a Zipf-like distribution. We expect that the result of this study will be a good guidance to design an efficient memory management policy for future smartphones.

• Journal of recreation and landscape
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• v.12 no.4
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• pp.45-58
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• 2018

Place memory is a new way of seeing as a new concept of cultural landscape research. Various research works and discussions have recently spread in landscape studies. In particular, the, which is visible and material, is a medium in which collective memory is embedded in place memory. The purpose of this study is to extract places of memory from the collective memory of residents of Janghang, Korea, and to visualize it through semantic relations. For this purpose, semi-standardized interviews (34 persons) were conducted with residents, and frequency analysis and semantic network analysis were used. As a result, the interviewees recalled only 127 places in Janghang that existed between 1920 and 2010. Locals remember the city based on places of memory. This means that the city could be illustrated according to specific places that are frequently mentioned. For instance, the top 25 places (top 20%) explain 65.6% of all the places in the city, and the top 39 places (top 30.8%) could describe 78.7% of the places. Some places are referred to more frequently when they are in the city's symbolic landscape, and the city's identity is projected on them. Some places were mentioned only infrequently but were nevertheless very important places by which to understand Janghang. These places of memory have not appeared in the documentary records before, which shows the value of the collective memory of the locals and the effectiveness of the interviewing method. In the clustering of the semantic network, six groups of places appeared. The local residents remembered the modern industrial city and recalled it in connection with the sites of daily life. This shows the possibility of looking not only at public memory and famous heritage as a macro history but also at daily life and meaningful places as a micro history about locals. This study has significance as an initial research that identified and visualized places of memory from the perspective of local residents. Such an approach could be useful in the study of everyday life and the conservation of modern heritage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.1-10
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• 2008

The present status of technical development of a highly scalable, high-speed non-volatile PCM is overviewed. Major technical challenges are described along with solutions that are being pursued in terms of innovative device structures and fabrication technologies, new phase change materials, and new memory schemes.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.391-397
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• 2015

Nonvolatile memories in memory hierarchy have been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU. In this paper, we study the use of a new type of nonvolatile memories - the Phase Change Memory (PCM) with a DRAM buffer system as the main memory. Our design reduced the total energy of a DRAM main memory of the same capacity by 80%. These results indicate that it is feasible to use PCM technology in place of DRAM in the main memory for better energy efficiency.

• Transactions of the Society of Information Storage Systems
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• v.2 no.4
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• pp.214-218
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• 2006

The focus and tracking servo system has been designed and proposed for the holographic memory of one dimensional spatial light modulator(SLM). The general servo method of conventional ODD system was based and modified for new holographic memory. The pre-grooved disc pattern and special dichroic coating were also included for new design in this research and the final separated optics are expected to be applied to the future general holographic memory as well as the one dimensional SLM holographic memory.

• ETRI Journal
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• v.32 no.4
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• pp.642-644
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• 2010

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.476-484
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• 2015

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.90-94
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• 2020

Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially, MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2298-2305
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• 2007

Many people is studying the embedded system. The embedded system becomes a small size device. The DOM memory is using in the mobile device and small site devices. This paper proposes light-weighted Linux O.S that is running onto the DOM memory. The embedded system with the DOM must have a light-weigthed O.S due to the memory space restriction. This paper designs light-weigthed Linux O.S for the DOM memory. The new designed LILO boot loader boots the new designed light-weigthed Linux O.S as a normal Linux O.S. This paper experiments comparing the designed new light-weigthed Linux O.S with a Linux PC.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.719-722
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• 1998

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.