Fast and Memory Efficient Method for Optimal Concurrent Fault Simulator

동시 고장 시뮬레이터의 메모리효율 및 성능 향상에 대한 연구

Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.