• 한국정보통신학회논문지
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• 제26권3호
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• pp.355-366
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• 2022

본 논문은 프로그램 가능한 구조를 사용하여 재구성이 가능하고 저 전력 초소형의 장점을 모두 제공하는 인공지능 가속기를 위한 마이크로코드 기반 뉴럴 네트워크 가속기 컨트롤러를 제안한다. 대상 가속기가 다양한 뉴럴 네트워크 모델을 지원하도록 마이크로코드 컴파일러를 통해 뉴럴 네트워크 모델을 마이크로코드로 변환하여 가속기의 메모리 접근과 모든 연산기를 제어할 수 있다. 200MHz의 System Clock을 기준으로 설계하였으며, YOLOv2-Tiny CNN model을 구동하도록 컨트롤러를 구현하였다. 객체 감지를 위한 VOC 2012 dataset 추론용 컨트롤러를 구현할 경우 137.9ms/image, mask 착용 여부 감지를 위한 mask detection dataset 추론용으로 구현할 경우 99.5ms/image의 detection speed를 달성하였다. 제안된 컨트롤러를 탑재한 가속기를 실리콘칩으로 구현할 때 게이트 카운트는 618,388이며, 이는 CPU core로서 RISC-V (U5-MC2)를 탑재할 경우 대비 약 65.5% 감소한 칩 면적을 제공한다.

• 전기전자학회논문지
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• 제21권4호
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• pp.420-423
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• 2017

본 논문에서는 렌더링 노이즈 제거를 위한 뉴럴 네트워크 가속기 구현을 제안한다. 렌더링 알고리즘 중에 고품질 그래픽스를 보장하는 레이트레이싱을 선택하였다. 레이트레이싱 렌더링은 레이를 사용해 렌더링을 한다. 레이를 적게 사용하게 되면 노이즈가 발생하게 되며, 많이 사용하게 되면 고화질의 이미지를 생성할 수 있으나 연산 시간이 길어진다. 이러한 레이트레싱 렌더링을 빠르게 처리하기 위해서 적게 레이를 사용하고 발생한 노이즈를 제거하는 알고리즘을 사용하게 된다. 그러한 알고리즘 중에 뉴럴 네트워크를 사용한 알고리즘이 있으며, 연산 속도를 빠르게 하기 위해서 연산에 사용되는 필터 파라미터를 구하는 뉴럴 네트워크 가속기를 구현했다. 하나의 픽셀에 사용되는 파라미터를 계산하기 위해 걸리는 시간은 11.44us 이다.

• Nuclear Engineering and Technology
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• 제41권10호
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• pp.1293-1306
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• 2009

In this paper, an infinite impulse response locally recurrent neural network (IIR-LRNN) is employed for modelling the dynamics of the Lead Bismuth Eutectic eXperimental Accelerator Driven System (LBE-XADS). The network is trained by recursive back-propagation (RBP) and its ability in estimating transients is tested under various conditions. The results demonstrate the robustness of the locally recurrent scheme in the reconstruction of complex nonlinear dynamic relationships.

• 전기학회논문지
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• 제58권10호
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• pp.2059-2063
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• 2009

This paper presents a programmable System-On-a-chip (SoC) for various embedded smart applications that need Neural Network computations. The system is fully implemented into a prototyping platform based on Field Programmable Gate Array (FPGA). The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using a real image processing application, an optical character recognition (OCR) system.

• 대한임베디드공학회논문지
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• 제17권6호
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• pp.367-374
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• 2022

The acceleration of neural networks has become an important topic in the field of computer vision. An accelerator is absolutely necessary for accelerating the lightweight model. Most accelerator-supported operators focused on direct convolution operations. If the accelerator does not provide GEMM operation, it is mostly replaced by CPU operation. In this paper, we proposed an optimization technique for 2-stage tiling-based GEMM routines on VTA. We improved performance of the matrix multiplication routine by maximizing the reusability of the input matrix and optimizing the operation pipelining. In addition, we applied the proposed technique to the DarkNet framework to check the performance improvement of the matrix multiplication routine. The proposed GEMM method showed a performance improvement of more than 2.4 times compared to the non-optimized GEMM method. The inference performance of our DarkNet framework has also improved by at least 2.3 times.

• 한국멀티미디어학회논문지
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• 제17권3호
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.

• 한국정보통신학회논문지
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• 제24권1호
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• pp.141-144
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• 2020

Convolutional neural networks (CNNs) show high performance in computer vision tasks including object detection, but a lot of weight storage and computation is required. In this paper, a pruning scheme is applied to CNNs for object detection, which can remove much amount of weights with a negligible performance degradation. Contrary to the previous ones, the pruning scheme applied in this paper considers the base accelerator architecture. With the consideration, the pruned CNNs can be efficiently performed on an ASIC or FPGA accelerator. Even with the constrained pruning, the resulting CNN shows a negligible degradation of detection performance, less-than-1% point degradation of mAP on VOD0712 test set. With the proposed scheme, CNNs can be applied to objection dtection efficiently.

• 전기전자학회논문지
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• 제20권3호
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• pp.303-306
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• 2016

본 논문에서는 GPGPU를 활용하여 Convolutional neural network의 가속화 방법을 제안한다. Convolutional neural network는 이미지의 특징 값을 학습하여 분류하는 neural network의 일종으로 대량의 데이터를 학습해야하는 영상 처리에 적합하다. 기존의 Convolutional neural network의 convolution layer는 다수의 곱셈 연산을 필요로 하여 임베디드 환경에서 실시간으로 동작하기에 어려움이 있다. 본 논문에서는 이러한 단점을 해결하기 위하여 winograd convolution 연산을 통하여 곱셈 연산을 줄이고 GPGPU의 SIMT 구조를 활용하여 convolution 연산을 병렬 처리한다. 실험은 ModelSim, TestDrive를 사용하여 진행하였고 실험 결과 기존의 convolution 연산보다 처리 시간이 약 17% 개선되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.685-686
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• 2007

This paper presents an application of power system fault diagnostic algorithm for the PEFP Proton Accelerator Research Center using neural network. Proposed fault diagnostic system is constructed by the radial basis function (RBF) neural network because it has the capabilities of the pattern classification and function approximation of any nonlinear function. Proposed system identifies faulted section in the power system based on information about the operation of protection devices such as relays and circuit breakers. In this paper, parameters of the RBF neural networks are tuned by the GA-TS algorithm, which has the global optimal solution searching capabilities. To show the validity of the proposed method, proposed algorithm has been tested with a practical power system in Proton Accelerator Research Center of PEFP.

• 디지털산업정보학회논문지
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• 제18권2호
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• pp.17-26
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• 2022

In this paper, we propose a novel method of performing convolutional operations on a 2-D Processing Element(PE) array. The conventional method [1] of mapping the convolutional operation using the 2-D PE array lacks flexibility and provides low utilization of PEs. However, by mapping a convolutional operation from a 2-D PE array to a 1-D PE array, the proposed method can increase the number and utilization of active PEs. Consequently, the throughput of the proposed Deep Convolutional Neural Network(DCNN) accelerator can be increased significantly. Furthermore, the power consumption for the transmission of weights between PEs can be saved. Based on the simulation results, the performance of the proposed method provides approximately 4.55%, 13.7%, and 2.27% throughput gains for each of the convolutional layers of AlexNet, VGG16, and ResNet50 using the DCNN accelerator with a (weights size) x (output data size) 2-D PE array compared to the conventional method. Additionally the proposed method provides approximately 63.21%, 52.46%, and 39.23% power savings.