• Advances in nano research
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• v.3 no.1
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• pp.49-54
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• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.132-132
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• 2009

A 2D-simulation using a quantum model of silicon nanowire (SiNW) field-effect transistors (FETs) have been performed by the effective mass theory. We have investigated very close for real device analysis, so we used to the non-equilibrium Green's function (NEGF) and the density gradient of quantum model. We investigated I-V characteristics curve and C-V characteristics curve of the channel thickness from 5nm to 200nm. As a result of simulation, even higher drain current in SiNW using a quantum model was observed than in SiNW using a non-quantum model. The reason of higher drain current can be explained by the quantum confinement effect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.49-56
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• 2008

This paper introduces a compact analytical current conduction model of long-channel depletion-mode n-type nanowire field-effect transistors (NWFETs). The NWFET used in this work was fabricated with the bottom-up process and it has a bottom-gate structure. The model includes all current conduction mechanisms of the NWFET operating at various bias conditions. The results simulated from the newly developed NWFET model reproduce a reported experimental results within a 10% error.

• Journal of the Korean Ceramic Society
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• v.45 no.4
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• pp.191-195
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• 2008

Highly ordered silver nanowire with a diameter of 10 nm was arrayed by electroless deposition in a porous anodic aluminum oxide(AAO) membrane. The AAO membrane was fabricated electrochemically in an oxalic acid solution via a two-step anodization process, while growth of the silver nanowire was initiated by using electroless deposition at the long-range-ordered nanochannels of the AAO membrane followed by thermal reduction of a silver nitrate aqueous solution by increasing the temperature up to $350^{\circ}C$ for an hour. An additional electro-chemical procedure was applied after the two-step anodization to control the pore size and channel density of AAO, which enabled us to fabricate highly-ordered silver nanowire on a large scale. Electroless deposition of silver nitrate aqueous solution into the AAO membrane and thermal reduction of silver nanowires was performed by increasing the temperature up to $350^{\circ}C$ for 1 h. The morphologies of silver nanowires arrayed in the AAO membrane were investigated using SEM. The chemical composition and crystalline structure were confirmed by XRD and EDX. The electroless-deposited silver nanowires in AAO revealed a well-crystallized self-ordered array with a width of 10 nm.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1297-1298
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• 2006

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have been attracted recently attention due to their highdevice performance expected from theoretical simulations among nanowire-based FETs with other gate geometries. OSG FETs with the channels of ZnO nanowires were successfully fabricated in this study with photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels of ZnO nanowires with diameters of about 60 nm are coated surroundingly by $Al_{2}O_{3}$ as gate dielectrics with atomic layer deposition. About 80 % of the surfaces of the nanowires coated with $Al_{2}O_{3}$ is covered with gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 98.9 $cm^{2}/Vs$, a peak transconductance of 0.4 ${\mu}S$, and an Ion/Ioff ratio of $10^6$ the value of the Ion/Ioff ratio obtained from this OSG FET is the highest among nanowire-based FETs, to our knowledge. Its mobility, peak transconductance, and Ion/Ioff ratio arc remarkably enhanced by 11.5, 32, and $10^6$ times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.200-200
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• 2009

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.413-413
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• 2009

Silicon nanowires (Si NWs)-based top-gate field-effect transistors (FETs) are constructed by using Si NWs transferred onto flexible plastic substrates. Si NWs are obtained from the silicon wafers using photolithography and anisotropic etching process, and transferred onto flexible plastic substrates. To evaluate the electrical performance of the silicon nanowires, we examined the output and transfer characteristics of a top-gate field-effect transistor with a channel composed of a silicon nanowire selected from the nanowires on the plastic substrate. From these FETs, a field-effect mobility and transconductance are evaluated to be $47\;cm^2/Vs$ and 272 nS, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.381-382
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• 2018

Subthreshold swings (SSs) and on-currents of four types of junctionless nanowire tunnel field-effect transistor(JLNW-TFET) are observed. Ge-Si structure for the source-channel junction has the highest drive current among Si-Si, Si-Ge, and Ge-Ge junction, and the drive current increases up to 1000 times compared to others. Minimum SS of Si-Si junction is reduced by up to 5 times more than others.

• Nanomaterials
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• v.12 no.10
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• pp.1721-1729
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• 2022

In this study, threshold voltage (V_th) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15-22 nm and various channel diameters (D_NW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of V_th (σV_th), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each D_NW, and σV_th was the smallest at a median D_NW of 9 nm. To analyze the observed D_NW tendency of σV_th, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (N_ch), and D_NW variations (WFV, ΔN_ch, and ΔD_NW) to σV_th were evaluated by directly fitting the developed model to measured σV_th. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σV_th. As D_NW decreased, SNWFETs became robust to ΔN_ch but vulnerable to ΔD_NW. Consequently, the contribution of ΔD_NW, WFV, and ΔN_ch is dominant at D_NW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of V_th variation, and it is applicable to all SNWFETs with various L_G and D_NW.