• 동력기계공학회지
• /
• 제17권1호
• /
• pp.110-115
• /
• 2013

The electrochemical performance and microstructure of Al-Si, Al-Si/C was investigated as anode for lithium ion battery. The Al-Si nano composite with 5 : 1 at% ratio was prepared by arc-discharge nano powder process. However, some of problem is occurred, when Al nano composite was synthesized by this manufacturing. The oxidation film is generated around Al-Si particles for passivating processing in the manufacture. The oxidation film interrupts electrical chemistry reaction during lithium ion insertion/extraction for charge and discharge. Because of the existence the oxidation film, Al-Si first cycle capacity is very lower than other examples. Therefore, carbon synthsized by glucose ($C_6H_{12}O_6$) was conducted to remove the oxidation film covered on the composite. The results showed that the first discharge cycle capacity of Al-Si/C is improved to 113mAh/g comparing with Al-Si (18.6mAh/g). Furthermore, XRD data and TEM images indicate that $Al_4C_3$ crystalline exist in Al-Si/C composite. In addition the Si-Al anode material, in which silicon is more contained was tested by same method as above, it was investigated to check the anode capacity and morphology properties in accordance with changing content of silicon, Si-Al anode has much higher initial discharge capacity(about 500mAh/g) than anode materials based on Aluminum as well as the morphology properties is also very different with the anode based Aluminum.

• 대한금속재료학회지
• /
• 제46권3호
• /
• pp.159-168
• /
• 2008

Thermally-evaporated 10 nm-Ni/1 nm-Ru/(30 nm or 70 nm-poly)Si structures were fabricated in order to investigate the thermal stability of Ru-inserted nickel monosilicide. The silicide samples underwent rapid thermal anne aling at $300{\sim}1,100^{\circ}C$ for 40 seconds. Silicides suitable for the salicide process were formed on the top of the single crystal and polycrystalline silicon substrates mimicking actives and gates. The sheet resistance was measured using a four-point probe. High resolution X-ray diffraction and Auger depth profiling were used for phase and chemical composition analysis, respectively. Transmission electron microscope and scanning probe microscope(SPM) were used to determine the cross-sectional structure and surface roughness. The silicide, which formed on single crystal silicon and 30 nm polysilicon substrate, could defer the transformation of $Ni_2Si $i and $NiSi_2 $, and was stable at temperatures up to $1,100^{\circ}C$ and $1,100^{\circ}C$, respectively. Regarding microstructure, the nano-size NiSi preferred phase was observed on single crystalline Si substrate, and agglomerate phase was shown on 30 nm-thick polycrystalline Si substrate, respectively. The silicide, formed on 70 nm polysilicon substrate, showed high resistance at temperatures >$700^{\circ}C$ caused by mixed microstructure. Through SPM analysis, we confirmed that the surface roughness increased abruptly on single crystal Si substrate while not changed on polycrystalline substrate. The Ru-inserted nickel monosilicide could maintain a low resistance in wide temperature range and is considered suitable for the nano-thick silicide process.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.241-241
• /
• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• 한국재료학회지
• /
• 제21권5호
• /
• pp.273-276
• /
• 2011

Ultraviolet (UV) light emitting diodes (LEDs) were grown on a patterned n-type GaN substrate (PNS) with 200 nm silicon-di-oxide (SiO2) nano pattern diameter to improve the light output efficiency of the diodes. Wet etched self assembled indium tin oxide (ITO) nano clusters serve as a dry etching mask for converting the SiO2 layer grown on the n-GaN template into SiO2 nano patterns by inductively coupled plasma etching. PNS is obtained by n-GaN regrowth on the SiO2 nano patterns and UV-LEDs were fabricated using PNS as a template. Two UV-LEDs, a reference LED without PNS and a 200 nm PNS UV-LEDs were fabricated. Scanning Electron microscopy (SEM), Transmission Electron Microscopy (TEM), X-Ray Diffraction (XRD), Photoluminescence (PL) and Light output intensity- Input current- Voltage (L-I-V) characteristics were used to evaluate the ITO-$SiO_2$ nanopattern surface morphology, threading dislocation propagation, PNS crystalline property, PNS optical property and UVLED device performance respectively. The light out put intensity was enhanced by 1.6times@100mA for the LED grown on PNS compared to the reference LED with out PNS.

• Current Photovoltaic Research
• /
• 제11권2호
• /
• pp.39-43
• /
• 2023

Carrier-selective contacts (CSCs) solar cells are considerably attractive on highly efficient crystalline silicon heterojunction (SHJ) solar cells due to their advantages of high thermal tolerance and the simple fabrication process. CSCs solar cells require a hole selective contact (HSC) layer that selectively collects only holes. In order to selectively collect holes, it must have a work function characteristic of 5.0 eV or more when contacted with n-type Si. The VO_x, NiO_x, and CuI_x thin films were fabricated and analyzed respectively to confirm their potential usage as a hole-selective contact (HSC) layer. All thin films showed characteristics of band-gap engergy > 3.0 eV, work function > 5.0 eV and minority carrier lifetime > 1.5 ms.

• 한국재료학회지
• /
• 제14권6호
• /
• pp.413-419
• /
• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• 대한금속재료학회지
• /
• 제48권7호
• /
• pp.660-666
• /
• 2010

30 nm thick Ni layers were deposited on a glass substrate by e-beam evaporation. Subsequently, 30 nm or 60 nm ${\alpha}-Si:H$ layers were grown at low temperatures ($<220^{\circ}C$) on the 30 nm Ni/Glass substrate by catalytic CVD (chemical vapor deposition). The sheet resistance, phase, microstructure, depth profile and surface roughness of the $\alpha-Si:H$ layers were examined using a four-point probe, HRXRD (high resolution Xray diffraction), Raman Spectroscopy, FE-SEM (field emission-scanning electron microscopy), TEM (transmission electron microscope) and AES depth profiler. The Ni layers reacted with Si to form NiSi layers with a low sheet resistance of $10{\Omega}/{\Box}$. The crystallinty of the $\alpha-Si:H$ layers on NiSi was up to 60% according to Raman spectroscopy. These results show that both nano-scale NiSi layers and crystalline Si layers can be formed simultaneously on a Ni deposited glass substrate using the proposed low temperature catalytic CVD process.

• 대한금속재료학회지
• /
• 제46권11호
• /
• pp.755-761
• /
• 2008

We fabricated thermally evaporated 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the energy saving property of silicides formed by rapid thermal annealing (RTA) at the temperature range of $300{\sim}1200^{\circ}C$ for 40 seconds. Moreover, we fabricated 100 nm-thick ITO/(poly)Si films with an rf-sputter as references. A transmission electron microscope (TEM) and an X-ray diffractometer were used to determine cross-sectional microstructure and phase changes. A UV-VIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were employed for near-IR and middle-IR absorbance. Through TEM analysis, we confirmed 20~65 nm-thick silicide layers formed on the single and polycrystalline silicon substrates. Ir-inserted nickel silicide on single crystalline substrate showed almost the same absorbance in near IR region as well as ITO, but Ir-inserted nickel silicide on polycrystalline substrate, which had the uniform absorbance in specific region, showed better absorbance in near IR region than ITO. The Ir-inserted nickel silicide on polycrystalline substrate particularly showed better absorbance in middle IR region than ITO. The results imply that nano-thick Ir-inserted nickel silicides may have excellent absorbing capacity in near-IR and middle-IR region.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
• /
• pp.192.1-192.1
• /
• 2015

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) and InGaZnOxide (IGZO) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment in gate insulator (SiO2). The whole memory fabrication process kept under $50^{\circ}C$ (except SiO2 deposition process; $300^{\circ}C$). These devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and H-NB CVD that we modified. Our study will further provide a vision of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

• 열처리공학회지
• /
• 제23권6호
• /
• pp.344-349
• /
• 2010

Silicon carbide nanowires were grown by heat treatment of the films at $1200^{\circ}C$ after amorphous SiC thin films were deposited on graphite substrate by radio frequency magnetron sputtering at $600^{\circ}C$. It was confirmed that SiC nanowires with the diameter of 20-60 nm and length of about 50nm were grown from Field Emission Scanning Election Microscope (FE-SEM) and Transmission Election Microscope (TEM) observation. The diameter of nanowires was increased as heat treatment time is increased. The nanowires were identified to ${\beta}$-SiC single crystalline from X-Ray Diffraction(XRD) analysis. It was observed from this study that deposition temperature of samples was critical to the crystallization of nanowires. On the other hand, the effect of deposition time was insignificant.