• Nanomaterials
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• v.12 no.7
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• pp.1061-1074
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• 2022

In this work, a self-powered, solar-blind photodetector, based on InZnSnO (IZTO) as a Schottky contact, was deposited on the top of Si-doped β-Ga₂O₃ by the sputtering of two-faced targets with InSnO (ITO) as an ohmic contact. A detailed numerical simulation was performed by using the measured J-V characteristics of IZTO/β-Ga₂O₃ Schottky barrier diodes (SBDs) in the dark. Good agreement between the simulation and the measurement was achieved by studying the effect of the IZTO workfunction, β-Ga₂O₃ interfacial layer (IL) electron affinity, and the concentrations of interfacial traps. The IZTO/β-Ga₂O₃ (SBDs) was tested at a wavelength of 255 nm with the photo power density of 1 mW/cm². A high photo-to-dark current ratio of 3.70×10⁵ and a photoresponsivity of 0.64 mA/W were obtained at 0 V as self-powered operation. Finally, with increasing power density the photocurrent increased, and a 17.80 mA/W responsivity under 10 mW/cm² was obtained.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Journal of the Korean Ceramic Society
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• v.52 no.6
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• pp.410-416
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• 2015

Recently, a new $Y_2O_3$ coating deposited using the EB-PVD method has been developed for erosion resistant applications in fluorocarbon plasma environments. In this study, surface crack formation in the $Y_2O_3$ coating has been analyzed in terms of residual stress and elastic modulus. The coating, deposited on silicon substrate at temperatures higher than $600^{\circ}C$, showed itself to be sound, without surface cracks. When the residual stress of the coating was measured using the Stoney formula, it was found to be considerably lower than the value calculated using the elastic modulus and thermal expansion coefficient of bulk $Y_2O_3$. In addition, amorphous $SiO_2$ and crystalline $Al_2O_3$ coatings were similarly prepared and their residual stresses were compared to the calculated values. From nano-indentation measurement, the elastic modulus of the $Y_2O_3$ coating in the direction parallel to the coating surface was found to be lower than that in the normal direction. The lower modulus in the parallel direction was confirmed independently using the load-deflection curves of a micro-cantilever made of $Y_2O_3$ coating and from the average residual stress-temperature curve of the coated sample. The elastic modulus in these experiments was around 33 ~ 35 GPa, which is much lower than that of a sintered bulk sample. Thus, this low elastic modulus, which may come from the columnar feather-like structure of the coating, contributed to decreasing the average residual tensile stress. Finally, in terms of toughness and thermal cycling stability, the implications of the lowered elastic modulus are discussed.

• Journal of Ceramic Processing Research
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• v.13 no.spc1
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• pp.149-153
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• 2012

Ti2AlN MAX-phase films were synthesized through the post-annealing process of as-deposited Ti-Al-N films. Near amorphous or quasi-crystalline ternary Ti-Al-N films were deposited on Si and Al2O3 substrates by sputtering a Ti2AlN MAX-phase target at room temperature, 300 ℃ and 450 ℃, respectively. A vacuum annealing of those films at 800 ℃ for 1 hour changed those films to crystalline Ti2AlN MAX-phase. The polycrystalline Ti2AlN MAX-phase films exhibited very excellent oxidation resistance due to its characteristics microstructure (nanolaminates), which has potential applications for high-temperature protective coatings. The microstructure and composition of Ti2AlN MAX-phase films were investigated using with a variety of characterization tools.

• Journal of Surface Science and Engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.39-45
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• 2012

Three-dimensional integrated circuit(3D IC) technology has become increasingly important due to the demand for high system performance and functionality. In this work, BOE and HF wet etching of Cu line surfaces after CMP were conducted for Cu-Cu pattern direct bonding. Step height of Cu and $SiO_2$ as well as Cu dishing after Cu CMP were analyzed by the 3D-Profiler. Step height increased and Cu dishing decreased with increasing BOE and HF wet etching times. XPS analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE and HF wet etching treatment. BOE treatment showed not only the effective $SiO_2$ etching but also reduced dishing and Cu surface oxide rather than HF treatment, which can be used as an meaningful process data for reliable Cu-Cu pattern bonding characteristics.

• Applied Chemistry for Engineering
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• v.34 no.6
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• pp.674-678
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• 2023

The effect of Pt was investigated to the catalytic methane decomposition of CH₄ to H₂ over Pt(1)-Fe(30)/MCM-41 and Fe(30)/MCM-41 using a fixed bed flow reactor under atmosphere. The Fe₂O₃ and Pt crystal phase behavior of fresh Pt(1)-Fe(30)/MCM-41 were obtained via XRD analysis. SEM, EDS analysis, and mapping were performed to show the uniformed distribution of nano particles such as Fe, Pt, Si, O on the catalyst surface. XPS results showed O^2-, O^- species and metal ions such as Pt⁰, Pt²⁺, Pt⁴⁺, Ft⁰, Fe²⁺, Fe³⁺ etc. When 1 wt% of Pt was added to Fe(30)/MCM-41, automic percentage of Fe2p increased from 13.39% to 16.14%, and Pt4f was 1.51%. The yield of hydrogen over Pt(1)-Fe(30)/MCM-41 was 3.2 times higher than Fe(30)/MCM-41. The spillover effect of H₂ from Pt to Fe increased the reduction of Fe particles and moderate interaction of Fe, Pt and MCM-41 increased the uniform dispersion of fine nanoparticles on the catalyst surface, and improved hydrogen yield.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.449-453
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• 2010

In this paper, the electrical characteristics of Fin-type SONOS(silicon-oxide-nitride-oxide-silicon) flash memory device with different trapping layers are analyzed in depth. Two kinds of trapping layers i.e., silicon nitride($Si_3N_4$) and hafnium oxide($HfO_2$) are applied. Compared to the conventional Fin-type SONOS device using the $Si_3N_4$ trapping layer, the Fin-type SOHOS(silicon-oxide-high-k-oxide-silicon) device using the $HfO_2$ trapping layer shows superior program/erase speed. However, the data retention properties in SOHOS device are worse than the SONOS flash memory device. Degraded data retention in the SOHOS device may be attributed to the tunneling leakage current induced by interface trap states, which are supported by the subthreshold slope and low frequency noise characteristics.

• Journal of the Korean Ceramic Society
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• v.41 no.4
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• pp.328-333
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• 2004

Hydroxyapatite (HAp) and HAp-Ag composite layers were coated on ZrO$_2$and Si wafer substrates by RF magnetron sputtering technique. The thickness of coating layers was in the range of 0.7∼1.0$\mu\textrm{m}$ and its roughness was 3∼4nm. The heat treated HAp coating layers were composed with nano-sized crystallines. However, the HAp-Ag composite layers showed the mixed structure with crystalline and amorphous phases. The Ca/P ratio of the as-received HAp coating layer was 1.9, but, the value was decreased as the Ag content with increased. Also, the Vickers hardness of HAp coating layer decreased as the Ag content increase.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.841-845
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• 2013

We give a textured front on silicon wafer for high-efficiency solar cells by using micro contact printing method which uses PDMS (polydimethylsiloxane) silicon rubber as a stamp and SAM (self assembled monolayer)s as an ink. A random pyramidal texturing have been widely used for a front-surface texturing in low cost manufacturing line although the cell with random pyramids on front surface shows relatively low efficiency than the cell with inverted pyramids patterned by normal optical lithography. In the past two decades, the micro contact printing has been intensively studied in nano technology field for high resolution patterns on silicon wafer. However, this promising printing technique has surprisingly never applied so far to silicon based solar cell industry despite their simplicity of process and attractive aspects in terms of cost competitiveness. We employ a MHA (16-mercaptohexadecanoic acid) as an ink for Au deposited $SiO_2/Si$ substrate. The $SiO_2$ pattern which is same as the pattern printed by SAM ink on Au surface and later acts as a hard resist for anisotropic silicon etching was made by HF solution, and then inverted pyramidal pattern is formed after anisotropic wet etching. We compare three textured surface with different morphology (random texture, random pyramids and inverted pyramids) and then different geometry of inverted pyramid arrays in terms of reflectivity.