• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.10
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• pp.799-806
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• 1991

Utilizing dual basis, normal basis, and subfield representation, three different finite field multipliers are presented in this paper. First, we propose an extended dual basis multiplier based on Berlekamp's bit-serial multiplication algorithm. Second, a detailed explanation and design of the Massey-Omura multiplier based on a normal basis representation is described. Third, the multiplication algorithm over GF(($2^{n}$) utilizing subfield is proposed. Especially, three different multipliers are designed over the finite field GF(($2^{4}$) and the complexity of each multiplier is compared with that of others. As a result of comparison, we recognize that the extendd dual basis multiplier requires the smallest number of gates, whereas the subfield multiplier, due to its regularity, simplicity, and modularlity, is easier to implement than the others with respect to higher($m{\ge}8$) order and m/2 subfield order.

• Journal of electromagnetic engineering and science
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• v.8 no.1
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• pp.17-22
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• 2008

It is presented that sampling rates for behavioral modeling of quasi-memory less nonlinear devices can be far less than the Nyquist rate of the input signal. Although it has been believed that the sampling rate of nonlinear device modeling should be at least the Nyquist rate of the output signal, this paper suggests that far less than the Nyquist rate of the input signal can be applied to the modeling of quasi-memoryless nonlinear devices, such as frequency multipliers. To verify, a QPSK signal at 820 MHz were applied to a frequency tripler, whereby the device can be utilized as an up-converting mixer into 2.46 GHz with the aid of digital predistortion. AM-AM, AM-PM and PM-PM can be successfully measured regardless of sampling rates.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.4
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• pp.467-473
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• 1996

This Paper presents a new algorithm to solve Dynamic Economic Dispatch problem. Proposed algorithm is composed of two computational modules; one is dispatch, the other adjusting module. In the dispatch module based on the traditional Static Economic Dispatch method, the power dispatch of each unit is calculated. And in case the results of dispatch module violate ramp rate constraints, Lagrange multipliers are adjusted in the adjusting module. Tests and computer results on test systems are given to show the efficiency of the proposed algorithm. (author). 11 refs., 6 figs., 4 tabs.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1561-1564
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• 2004

A CMOS-based Electronically Tunable Capacitance Multipliers, which can be magnified the value of a grounded unit capacitance, is presented in this article. The multiplication factor is varied by the ratio of the bias currents. The proposed circuit is simple, small in size and suitable for implementing in standard CMOS process. PSPICE simulation results demonstrating the characteristics of the proposed circuit are included.

• Bulletin of the Korean Mathematical Society
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• v.50 no.3
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• pp.915-928
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• 2013

In this paper, we will provide an alternative proof to characterize the pointwise multipliers which maps a Sobolev space $\dot{H}^r(\mathb{R}^d)$ to its dual $\dot{H}^{-r}(\mathb{R}^d)$ in the case 0 < $r$ < $\frac{d}{2}$ by a simple application of the definition of fractional Sobolev space. The proof relies on a method introduced by Maz'ya-Verbitsky [9] to prove the same result.

• Journal of the Chungcheong Mathematical Society
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• v.22 no.4
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• pp.727-737
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• 2009

Let M(X) be the space of all pointwise multipliers of Banach space X. We will show that, for each $\alpha>1$, $M(\mathfrak{B}_\alpha)=M(\mathfrak{B}_{\alpha,0})=H^\infty{(B)}$. We will also show that, for each $0<{\alpha}<1$, $M(\mathfrak{B}_\alpha)$ and $M(\mathfrak{B}_{\alpha,0})$ are Banach algebras. It is established that certain inclusion relationships exist between the weighted Bloch spaces and holomorphic Besov spaces.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.277-280
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• 2002

This paper analyze the characteristics of three multipliers in finite fields GF(2m) from the point of view of processing time and area complexity. First, we analyze structure of three multipliers; 1) LSB-first systolic array, 2) LFSR structure, and 3) CA structure. To make performance analysis, each multiplier was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that LFSR structure is best from the point of view of area complexity, and LSB systolic array is best from the point of view of processing time per clock.

• Journal of the Chungcheong Mathematical Society
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• v.29 no.3
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• pp.443-451
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• 2016

In this paper, we introduce the concept of a symmetric bi-f-multiplier in incline algebras and give some properties of incline algebras. Also, we characterize Ker(D) and $Fix_a(D)$ by symmetric bi-f-multipliers in incline algebras.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.5
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• pp.398-406
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• 1991

This paper presents a graphics accelerator for fast image generation. The accelarator has three major functional blocks: linear interpolator, multipliers and Edgee Painting Tree. Linear interpolator with coupled binary tree structure interpolates functional values of two end points. Two multipliers compute input values of interpolator in parallel. Mask pattern which removes out invalid data is generated by Edge Painting Tree. The proposed architecture in this paper is responsible for 64 pixels and can process about 5,900 10x10polygons per second.