• Kyungpook Mathematical Journal
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• 제46권1호
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• pp.97-109
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• 2006

In this paper, the authors introduce new classes of p-valent functions defined by Dziok-Srivastava linear operator and the multiplier transformation and study their properties by using certain first order differential subordination and superordination. Also certain inclusion relations are established and an integral transform is discussed.

• East Asian mathematical journal
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• 제16권2호
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• pp.225-231
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• 2000

The purpose of the present paper is to introduce a new class $\mathcal{P}_{n,p}(\alpha)$ of analytic functions defined by a multiplier transformation and to investigate some properties for the class $\mathcal{P}_{n,p}(\alpha)$.Furthermore, we consider an integral of functions belonging to the class $\mathcal{P}_{n,p}(\alpha)$.

• East Asian mathematical journal
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• 제27권3호
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• pp.299-308
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• 2011

The purpose of the present paper is to obtain some subordination and superordination preserving properties involving a certain family of multiplier transformations for meromorphic functions in the open unit disk. The sandwich-type theorems for these linear operators are also considered.

• 전자공학회논문지
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• 제51권6호
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• pp.117-123
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• 2014

본 논문에서는 기저변환을 사용하여 효율적인 곱셈기를 구성하는 방법을 제안하였다. 제안한 곱셈기는 두 입력부분 중 한 입력을 듀얼기저로 변환하는 표준-듀얼 기저 변환회로 모듈과 주어진 m차 기약다항식에 의해 $b_m$부터 $b_{m+k}$를 발생시키는 $b_{m+k}$차 발생연산모듈, $m^2$개의 AND 게이트와 m(m-1)개의 EX-OR 게이트로 구성되는 다항식 승산모듈로 구성된다. 또한, 듀얼기저로 표현되는 출력부분을 표준기저로 변화시켜주는 듀얼-표준 기저 변환회로 모듈로 구성되며, 각 연산부의 구성에 필요한 기본 연산모듈을 정의하였다.

• 대한임베디드공학회논문지
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• 제4권1호
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• pp.1-8
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• 2009

This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

• Kyungpook Mathematical Journal
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• 제49권1호
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• pp.47-55
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• 2009

In the present investigation sufficient conditions are found for certain subclass of normalized analytic functions defined by Hadamard product. Differential sandwich theorems are also obtained. As a special case of this we obtain results involving Ruscheweyh derivative, S$\u{a}$l$\u{a}$gean derivative, Carlson-shaffer operator, Dziok-Srivatsava linear operator, Multiplier transformation.

• 대한수학회보
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• 제40권3호
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• pp.399-410
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• 2003

The purpose of the present paper is to introduce some new subclasses of strongly close-to-convex functions in the open unit disk defined by multiplier transformations and study their properties. Our results include several previous known results as special cases.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2004년도 춘계학술대회
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• pp.706-709
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• 2004

A numerical method was developed that imposes constraint condition on the order parameters in martensitic phase transformation. In the method, an amplitude function having values of 1 or 0 was multiplied to transformation rates. The merit of the method is that the imposition of the constraint condition is more straightforward than a method with Lagrangian multiplier and easy to implement in the tangent modulus method. The developed method is applied to three-dimensional finite element analyses of single and poly crystalline shape memory alloys.

• 전자공학회논문지
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• 제53권2호
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• pp.70-75
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• 2016

본 논문에서는 다항식에 기초하여 유한체상의 P=2인 경우의 효율적인 곱셈기를 구성하는 방법을 제안하였다. 제안한 곱셈기 회로는 다항식의 연산부와 mod F(${\alpha}$) 연산부, 모듈러 연산부로 구성된다. 또한, 이들 각 연산부는 모듈 구조를 가지므로 m의 확장에 따른 회로 구성이 용이하며 회로 구성에 사용한 소자는 AND 게이트와 XOR 게이트만으로 구성하여 정규성, 확장성이 용이하며 이를 기반으로 VLSI화에 적합하다. 제안한 곱셈기는 기존의 곱셈기에 비해 좀 더 콤펙트, 규칙적, 정규성과 확장성이 용이하며 최근의 IoT 환경에서의 여러 분야에 적용 및 응용이 가능할 것이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.