• Kyungpook Mathematical Journal
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• v.46 no.1
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• pp.97-109
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• 2006

In this paper, the authors introduce new classes of p-valent functions defined by Dziok-Srivastava linear operator and the multiplier transformation and study their properties by using certain first order differential subordination and superordination. Also certain inclusion relations are established and an integral transform is discussed.

• East Asian mathematical journal
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• v.16 no.2
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• pp.225-231
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• 2000

The purpose of the present paper is to introduce a new class $\mathcal{P}_{n,p}(\alpha)$ of analytic functions defined by a multiplier transformation and to investigate some properties for the class $\mathcal{P}_{n,p}(\alpha)$.Furthermore, we consider an integral of functions belonging to the class $\mathcal{P}_{n,p}(\alpha)$.

• East Asian mathematical journal
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• v.27 no.3
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• pp.299-308
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• 2011

The purpose of the present paper is to obtain some subordination and superordination preserving properties involving a certain family of multiplier transformations for meromorphic functions in the open unit disk. The sandwich-type theorems for these linear operators are also considered.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.117-123
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• 2014

This paper proposes the constructing method of effective multiplier using basis transformation. Th proposed multiplier is composed of the standard-dual basis transformation circuit module to change one input into dual basis the operation module to generate from bm to bm+k by the m degree irreducible polynomial, and the polynomial multiplicative module to consist of $m^2$ AND and m(m-1) EX-OR gates. Also, the dual-standard basis transformation circuit module to change the output part to be shown as a dual basis into standard basis is composed. The operation modules to need in each operational part are defined.

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.1
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• pp.1-8
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• 2009

This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

• Kyungpook Mathematical Journal
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• v.49 no.1
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• pp.47-55
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• 2009

In the present investigation sufficient conditions are found for certain subclass of normalized analytic functions defined by Hadamard product. Differential sandwich theorems are also obtained. As a special case of this we obtain results involving Ruscheweyh derivative, S$\u{a}$l$\u{a}$gean derivative, Carlson-shaffer operator, Dziok-Srivatsava linear operator, Multiplier transformation.

• Bulletin of the Korean Mathematical Society
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• v.40 no.3
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• pp.399-410
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• 2003

The purpose of the present paper is to introduce some new subclasses of strongly close-to-convex functions in the open unit disk defined by multiplier transformations and study their properties. Our results include several previous known results as special cases.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.706-709
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• 2004

A numerical method was developed that imposes constraint condition on the order parameters in martensitic phase transformation. In the method, an amplitude function having values of 1 or 0 was multiplied to transformation rates. The merit of the method is that the imposition of the constraint condition is more straightforward than a method with Lagrangian multiplier and easy to implement in the tangent modulus method. The developed method is applied to three-dimensional finite element analyses of single and poly crystalline shape memory alloys.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.70-75
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• 2016

This paper proposes the constructing method of effective multiplier based on the finite fields in case of P=2. The proposed multiplier is constructed by polynomial arithmetic part, mod F(${\alpha}$) part and modular arithmetic part. Also, each arithmetic parts can extend according to m because of it have modular structure, and it is adopted VLSI because of use AND gate and XOR gate only. The proposed multiplier is more compact, regularity, normalization and extensibility compare with earlier multiplier. Also, it is able to apply several fields in recent hot issue IoT configuration.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.