• Journal of IKEEE
• /
• v.19 no.3
• /
• pp.378-384
• /
• 2015

In conventional HEVC inverse core transform architectures, extra $n{\times}n$ inverse transform block is added to $2n{\times}2n$ inverse transform block, and it operates as one $2n{\times}2n$ inverse transform block or two $n{\times}n$ inverse transform blocks. Thus, same number of pixels are processed in the same time, but it suffers from increased hardware size due to extra $n{\times}n$ inverse transform block. To avoid this problem, a novel $8{\times}8$ HEVC inverse core transform architecture was proposed to eliminate extra $4{\times}4$ inverse transform block based on multiplier reuse. This paper extends this approach and proposes a novel HEVC $16{\times}16$ inverse core transform architecture. Its frame processing time is same in $4{\times}4$, $8{\times}8$, and $16{\times}16$ inverse core transforms, and reduces gate counts by 13%.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.16 no.8
• /
• pp.2816-2830
• /
• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• Kyungpook Mathematical Journal
• /
• v.49 no.4
• /
• pp.631-646
• /
• 2009

In the present investigation, we introduce new classes of p-valent meromorphic functions defined by Liu-Srivastava linear operator and the multiplier transform and study their properties by using certain first order differential subordination and superordination.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.101-109
• /
• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• East Asian mathematical journal
• /
• v.16 no.2
• /
• pp.225-231
• /
• 2000

The purpose of the present paper is to introduce a new class $\mathcal{P}_{n,p}(\alpha)$ of analytic functions defined by a multiplier transformation and to investigate some properties for the class $\mathcal{P}_{n,p}(\alpha)$.Furthermore, we consider an integral of functions belonging to the class $\mathcal{P}_{n,p}(\alpha)$.

• Kyungpook Mathematical Journal
• /
• v.46 no.1
• /
• pp.97-109
• /
• 2006

In this paper, the authors introduce new classes of p-valent functions defined by Dziok-Srivastava linear operator and the multiplier transformation and study their properties by using certain first order differential subordination and superordination. Also certain inclusion relations are established and an integral transform is discussed.

• Journal of Advanced Navigation Technology
• /
• v.7 no.2
• /
• pp.141-148
• /
• 2003

This paper presents and compares several techniques that detect the symbol rate of unknown received signal. Symbol rate is detected from the power spectral density of the circuits such as the delay and multiplier circuit, the square law circuit, and analytic signal, etc. As a result of discrete Fourier transform of the output signals of these circuits, a lot of spectral lines and some peaks appear in frequency domain and the position of first peak is corresponding to the symbol rate. If a spectral line on the frequency that is not located in symbol rate is larger than the first peak, the symbol rate is erroneously detected. Thus, the ratio between the value of first peak and the highest side spectral line is used for the measure of the performance of symbol rate detector. For the MPSK modulation, the analytic signal method shows better performance than the delay and multiplier and square law circuits when the received signal power is lager than -20dB. It is also noted that the delay and multiplier circuit is not able to detect the symbol rate for the QAM modulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.1
• /
• pp.78-83
• /
• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.362-364
• /
• 2001

This paper presents the establishment of the wavelet transform domain sign algorithm and performance analysis by using wavelet filter such as multiplier-free QMF which don't require multiple computation.

• Journal of IKEEE
• /
• v.17 no.4
• /
• pp.570-578
• /
• 2013

This paper proposed an $8{\times}8$ HEVC inverse core transform architecture reusing multipliers. In HEVC core transform, processing of lower size block is identical with even part of upper size block. So an $8{\times}8$ core transform architecture can process both $8{\times}8$ and $4{\times}4$ core transforms. However, when $8{\times}8$ core transform architecture is exploited, frame processing time doubles in $4{\times}4$ core transform, since $8{\times}8$ and $4{\times}4$ core transforms concurrently process 8 and 4 pixels, respectively. In this paper, a novel inverse core transform architecture is proposed based on multiplier reuse. It runs as an $8{\times}8$ inverse core transformer or two $4{\times}4$ inverse core transformer. Its frame processing time is same in $8{\times}8$ and $4{\times}4$ core transforms, and reduces gate counts by 12%.