• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.802-805
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• 2007

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

• 대한전자공학회논문지
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• 제18권6호
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• pp.9-15
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• 1981

다출력 TANT회로망에 대한 구성게이트수와 이들의 상호연결에 관계되는 게이트입력수를 최소화시키는 새로운 방법이 제시되었다. 본 연구에서는 다출력맵(multiple-output map)을 구성하여 헤드변수의 갯수가 작은 순서에 따라 통합 개념을 적용하여 최적함수를 구성하였다. 조직적인 통합은 PSA(position search algorithm)에 의했으며 이로써 전체적인 설계자정을 줄일 수 있었다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권6호
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• pp.1620-1634
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• 2023

This paper studies the task of embedding nodes with multiple graphs representing multiple information channels, which is useful in a large volume of network clustering tasks. By learning a node using multiple graphs, various characteristics of the node can be represented and embedded stably. Existing studies using multi-channel networks have been conducted by integrating heterogeneous graphs or limiting common nodes appearing in multiple graphs to have similar embeddings. Although these methods effectively represent nodes, it also has limitations by assuming that all networks provide the same amount of information. This paper proposes a method to overcome these limitations; The proposed method gives different weights according to the source graph when embedding nodes; the characteristics of the graph with more important information can be reflected more in the node. To this end, a novel method incorporating a multi-channel gate layer is proposed to weigh more important channels and ignore unnecessary data to embed a node with multiple graphs. Empirical experiments demonstrate the effectiveness of the proposed multi-channel-based embedding methods.

• 전기전자학회논문지
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• 제3권1호
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• pp.50-56
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• 1999

본 논문은 정밀한 클락 지연을 발생하는 회로 기법을 제안하였다. 이 기법은 지연 체인을 다중 클락 주기에 록킹(Locking)시켜서 개별 지연단(Delay Stage)의 지연보다 작은 지연 해상도를 갖도록 하는 것이다. 이 기법으로 단위 셀이 750ps의 지연시간을 갖는 지연체인에서 DLL(Delay Locked Loop)을 이용하여 250ps의 지연간격을 갖는 지연 발생회로를 설계하였다. 제안한 회로는 지연체인이 클락 신호 주기의 3배에 록킹이 되도록 하였으며, 1.5um CMOS공정의 모의 실험을 통해 단위지연셀 지연시간의 1/3인 250ps의 지연간격을 발생함을 확인하였다.

• 전기학회논문지
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• 제61권4호
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• pp.522-533
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• 2012

This paper presents an adaptive strategy of GENCOs for reducing the greenhouse gas by fuel mix change. Fuel mix stands for generation capacity portfolio composed of different fuel resources. Currently, the generation sector of power industry in Korea is heavily dependent on fossil fuels, therefore it is required to change the fuel mix gradually into more eco-friendly way based on renewable energies. The generation costs of renewable energies are still expensive compared to fossil fueled resources. This is why the adaptive change is more preferred at current stage and this paper proposes an optimal strategy for capacity planning based on multiple environmental scenarios on the time horizon. This study used the computer program tool named GATE-PRO (Generation And Transmission Expansion PROgram), which is a mixed-integer non-linear program developed by Hongik university and Korea Energy Economics Institute. The simulations have been carried out with the priority allocation method in the program to determine the optimal mix of NRE(New Renewable Energy). Through this process, the result proposes an economic fuel mix under emission constraints compatible with the greenhouse gas mitigation policy of the United Nations.

• 전자공학회논문지C
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• 제35C권7호
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• pp.78-91
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• 1998

This paper presents modular design techniques of multiple-valued logic functions about the function decomposition method and input variable management method. The function decomposition method takes avantage of the property of the column multiplicity in a single-column variable partitioning. Due to the increased number of identical modules, we can achieve a simpler circuit design by using a single T-gate, which can eliminate some of the control functions in the module libraty types. The input variable management method is to reduce the complexity of the input variables by proposing the look up table which assign input variables to a code. In this case as the number of sub-functions increase the code-length and the size of the code-assignment table grow. We identify some situations where shard input variables among sub-functions can be further reduced by a simplicication technique. According to the result of adapting this method to a function, we have demonstrated the superiority of the proposed methods which is bing decreased to about 12% of interconnection and about 16% of T-gate numbers compare with th eexisting for th enon-symmetric and irregular function realization.

• 한국통신학회논문지
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• 제22권11호
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• 한국전자통신학회논문지
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• 제12권1호
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• pp.101-108
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• 2017

양자게이트 행렬은 치수가 r, 제어상태벡터 수가 n 및 표적상태벡터 수가 1인 경우에 $r^{n+1}{\times}r^{n+1}$ 차원 행렬이므로 n 증가에 따른 행렬 크기는 지수 함수적 증가 특성을 갖는다. 만약 제어상태벡터의 경우 수가 $2^n$이라면 $2^n-1$ 경우는 입력이 출력에 보전되는 단위행렬의 항등연산이고, 오직 한 개의 제어상태벡터 연산만이 표적상태벡터에 대한 유니터리 연산이다. 본 논문은 행렬차원 증가에 결정적 기여를 하는 $2^n-1$개의 단위행렬 연산을 한 동작의 산술멱승 연산으로 대체할 수 있는 새로운 함수 임베딩 방법을 제안한다. 제안한 함수 임베딩 방법은 다치 임계값을 갖는 2진 리터럴 스위치를 사용하므로 범용 하이브리드 MCU 게이트를 $r{\times}r$ 유니터리 행렬로 실현할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.