• Title/Summary/Keyword: multiple gate

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Isolated Power Supply for Multiple Gate Drivers using Wireless Power Transfer System with Single-Antenna Receiver

  • Lim, Chang-Jong;Park, Shihong
    • Journal of Power Electronics
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    • v.17 no.5
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    • pp.1382-1390
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    • 2017
  • This paper presents a power supply for gate drivers, which uses a magnetic resonance wireless power transfer system. Unlike other methods where multiple antennas are used to supply power for the gate drivers, the proposed method uses a single antenna in an insulated receiver to make multiple mutually isolated power supplies. The power transmitted via single antenna is distributed to multiple power supplies for gate drivers through resonant capacitors connected in parallel that also block DC bias. This approach has many advantages over other methods, where each gate driver needs to be supplied with power using multiple receiver antennas. The proposed method will therefore lead to a reduction in production costs and circuit area. Because the proposed circuit uses a high resonance frequency of 6.78 MHz, it is possible to implement a transmitter and a receiver using a small-sized spiral printed-circuit-board-type antenna. This paper used a single phase-leg circuit configuration to experimentally verify the performance characteristics of the proposed method.

Development of Gate Structure in Junctionless Double Gate Field Effect Transistors (이중게이트 구조의 Junctionless FET 의 성능 개선에 대한 연구)

  • Cho, Il Hwan;Seo, Dongsun
    • Journal of IKEEE
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    • v.19 no.4
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    • pp.514-519
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    • 2015
  • We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

Realization of Multiple-Control Toffoli gate based on Mutiple-Valued Quantum Logic (다치양자논리에 의한 다중제어 Toffoli 게이트의 실현)

  • Park, Dong-Young
    • Journal of Advanced Navigation Technology
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    • v.16 no.1
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    • pp.62-69
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    • 2012
  • Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

A Study on Construction of Multiple-Valued Multiplier over GF($p^m$) using CCD (CCD에 의한 GF($p^m$)상의 다치 승산기 구성에 관한 연구)

  • 황종학;성현경;김흥수
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.3
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    • pp.60-68
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    • 1994
  • In this paper, the multiplicative algorithm of two polynomials over finite field GF(($p^{m}$) is presented. Using the presented algorithm, the multiple-valued multiplier of the serial input-output modular structure by CCD is constructed. This multiple-valued multiplier on CCD is consisted of three operation units: the multiplicative operation unit, the modular operation unit, and the primitive irreducible polynomial operation unit. The multiplicative operation unit and the primitive irreducible operation unit are composed of the overflow gate, the inhibit gate and mod(p) adder on CCD. The modular operation unit is constructed by two mod(p) adders which are composed of the addition gate, overflow gate and the inhibit gate on CCD. The multiple-valued multiplier on CCD presented here, is simple and regular for wire routing and possesses the property of modularity. Also. it is expansible for the multiplication of two elements on finite field increasing the degree mand suitable for VLSI implementation.

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A Study on the Constructions MOVAGs based on Operation Algorithm for Multiple Valued Logic Function and Circuits Design using T-gate (다치 논리 함수 연산 알고리즘에 기초한 MOVAG 구성과 T-gate를 이용한 회로 설계에 관한 연구)

  • Yoon, Byoung-Hee;Park, Soo-Jin;Kim, Heung-Soo
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.22-32
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    • 2004
  • In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

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A Gate Delay Model Considering Temporal Proximity of Multiple Input Switching (다중 입력 변화의 시간적 근접성을 고려한 게이트 지연 시간 모델)

  • Shin, Jang-Hyuk;Kim, Ju-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.32-39
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    • 2010
  • Conventional cell characterization does not consider Multiple Input Switching(MIS). Since the impact of MIS on gate delay variation is large, it is not possible to predict the accurate gate delay with the conventional cell characterization. We observed the maximum 46% difference in gate delay due tn MIS. In this paper, we propose a gate delay model considering the delay variation caused by the temporal proximity of MIS. The proposed model calculates the delay variation using the Radial Basis Function. The experimental results show that the proposed method can more accurately predict the gate delay when MIS occurs.

A Highly Power-Efficient Single-Inductor Multiple-Outputs (SIMO) DC-DC Converter with Gate Charge Sharing Method

  • Nam, Ki-Soo;Seo, Whan-Seok;Ahn, Hyun-A;Jung, Young-Ho;Hong, Seong-Kwan;Kwon, Oh-Kyong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.549-556
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    • 2014
  • This paper proposes a highly power-efficient single-inductor multiple-outputs (SIMO) DC-DC converter with a gate charge sharing method in which gate charges of output switches are shared to improve the power efficiency and to reduce the switching power loss. The proposed converter was fabricated by using a $0.18{\mu}m$ CMOS process technology with high voltage devices of 5 V. The input voltage range of the converter is from 2.8 V to 4.2 V, which is based on a single cell lithium-ion battery, and the output voltages are 1.0 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V. Using the proposed gate charge sharing method, the maximum power efficiency is measured to be 87.2% at the total output current of 450 mA. The measured power efficiency improved by 2.1% compared with that of the SIMO DC-DC converter without the proposed gate charge sharing method.

Reliability of Multiple Oxides Integrated with thin $HfSiO_x$ gate Dielectric on Thick $SiO_2$ Layers

  • Lee, Tae-Ho;Lee, B.H.;Kang, C.Y.;Choi, R.;Lee, Jack-C.
    • Journal of the Microelectronics and Packaging Society
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    • v.15 no.4
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    • pp.25-29
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    • 2008
  • Reliability and performance in metal gate/high-k device with multiple gate dielectrics were investigated. MOSFETs with a thin $HfSiO_x$ layer on a thermal Si02 dielectric as gate dielectrics exhibit excellent mobility and low interface trap density. However, the distribution of threshold voltages of $HfSiO_x/SiO_2$ stack devices were wider than those of $SiO_2$ and $HfSiO_x$ single layer devices due to the penetration of Hf and/or intermixing of $HfSiO_x$ with underlying $SiO_2$. The results of TZDB and SILC characteristics suggested that a certain portion of $HfSiO_x$ layer reacted with the underlying thick $SiO_2$ layer, which in turn affected the reliability characteristics.

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Impact of Fin Aspect Ratio on Short-Channel Control and Drivability of Multiple-Gate SOI MOSFET's

  • Omura, Yasuhisa;Konishi, Hideki;Yoshimoto, Kazuhisa
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.302-310
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    • 2008
  • This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

A Generalized Coding Algorithm for m Input Radix p Shadow-Casting Optical Logic Gate (다중입력 Shawdow-Casting광 논리게이트를 위한 코딩방식의 일반화)

  • 최도형;권원현;박한규
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.8
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    • pp.992-997
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    • 1988
  • A generalized coding algorithm for multiple inputs multiple-valued logic gate based on shadow-casting is proposed. Proposed algorithm can minimize the useless pixels in case the number of inputs is not 2N (N is a natural number). A detailed analysis of advantages of proposed algorithm is presented and its effectiveness is demonstrated in case of three input binary system using inputs of 8*8 data.

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