• The KIPS Transactions:PartA
• /
• v.18A no.2
• /
• pp.45-52
• /
• 2011

In the past, a patient went to the room where an ultrasound image diagnosis device was set, and then he or she was examined by a doctor. However, currently a doctor can go and examine the patient with a handheld ultrasound device who stays in a room. However, it was implemented with only fundamental functions, and can not meet the high performance required by the focusing algorithm of ultrasound beam which determines the quality of ultrasound image. In addition, low energy consumption was satisfied for the mobile ultrasound device. To satisfy these requirements, this paper proposes a high-performance and low-power single instruction, multiple data (SIMD) based multi-core processor that supports a representative beamforming algorithm out of several focusing methods of mobile ultrasound image signals. The proposed SIMD multi-core processor, which consists of 16 processing elements (PEs), satisfies the high-performance required by the beamforming algorithm by exploiting considerable data-level parallelism inherent in the echo image data of ultrasound. Experimental results showed that the proposed multi-core processor outperforms a commercial high-performance processor, TI DSP C6416, in terms of execution time (15.8 times better), energy efficiency (6.9 times better), and area efficiency (10 times better).

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.12
• /
• pp.2140-2145
• /
• 2008

We design and synthesize a 128-point FFT processor for multi-band OFDM, which can be applied to a UWB transceiver. The structure of a 128-point FFT processor is based on a Radix-2 FFT algorithm and a R2SDF pipeline architecture. The algorithm is efficiently modeled in VHDL and the result is simulated using Modelsim. Finally, they are synthesized on Xilinx Vertex-II FPGA, and an operational frequency of 18.7MHz has been obtained. It is expected that the proposed 128-point FFT processor can be applied to an entire FFT block as one of parallel processed FFTs. In order to obtain the enhanced maximum frequency of operation, we design the FFT module consisting of four 128-point FFT processors for parallel process. As a result, we achieve the performance requirement of computing the FFT module in multi-band OFDM symbol timing in 90nm ASIC process.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.19 no.4
• /
• pp.119-128
• /
• 2019

Due to the nature of the 3D graphics processor system, many mathematical calculations are required and parallel processing research using GPU (Graphics Processing Unit) is being performed for high-speed processing. In this paper, we propose a 3D graphics processor using MAMS, a parallel processor that does not use cache memory, to solve the GPU problem of increasing bandwidth caused by cache memory miss and the problem that 3D shader processing speed is not constant. The 3D graphics processor using MAMS proposed in this paper designed Vertex shader, Pixel shader, Tiling and Rasterizing structure using DirectX command analysis, the FPGA(Xilinx Virtex6@100MHz) board for MAMS was constructed and designed using Verilog. We compared the processing time of the developed FPGA (100Mhz) and nVidia GeForce GTX 660 (980Mhz), the processing time using GTX 660 was not constant and suing MAMS was constant.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.2
• /
• pp.97-102
• /
• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Journal of Advanced Navigation Technology
• /
• v.23 no.2
• /
• pp.134-141
• /
• 2019

Radar systems are divided into the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar depending on the transmission waveform. In particular, the PD radar is advantageous for long-range target detection, and the FMCW radar is suitable for short-range target detection. In this paper, we present design and implementation results for a multi-mode radar signal processor (RSP) that can support both PD and FMCW radar systems to detect unmanned aerial vehicles (UAVs) at short distances as well as long distances. The proposed radar signal processor can be implemented based on Altera Cyclone-IV FPGA with 19,623 logic elements, 9,759 registers, and 25,190,400 memory bits. The logic elements and registers of the proposed radar signal processor are reduced by approximately 43% and 30%, respectively, compared to the sum of logic elements and registers of the conventional PD radar and FMCW radar signal processor.

• Journal of Power Electronics
• /
• v.9 no.3
• /
• pp.410-417
• /
• 2009

This paper represents a design and implementation of a digital controller for a multi-phase synchronous buck converter (SBC) using a digital signal processor (DSP). The multi-phase SBC has generally been used for a voltage regulation module (VRM) of a microprocessor because of its high current handling capability at a low output voltage. The VRM requires high control performance of tight output regulation, high slew rate, and load sharing capability of multiple converters. In order to achieve these requirements, the design and implementation of a digital control system for a multi-phase SBC are presented in this paper. The digital PWM generation, current sensing, and voltage and current controller using a DSP TMS320F2812 are considered. The experimental results are provided to show the validity of the implemented digital control system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.11
• /
• pp.1171-1177
• /
• 2009

A missile warning radar is an essential sensor for active protection system to detect antitank missile in all weather environments. This paper introduces missile warning radar for main battle tank and presents the results of the design and implementation of the radar signal processor using high speed multi-DSP. The key algorithms include adaptive CF AR, weighted linear fitting algorithm, S/W tracking capability, and threat decision and present test result.

• Proceedings of the KIEE Conference
• /
• 2002.11c
• /
• pp.23-26
• /
• 2002

In this paper, we modelize several scheduling algorithms for real-time packet filtering tasks based on the multi-threaded multi-processor architecture for the network security system like the firewall and compare the performance of the algorithms by implementing the algorithms and doing a number of empirical tasks. As the matrices of the performance we use the idle factor and the packet transfer rate. We get the idle factors and the packet transfer rates according to the transfers of the packet sizes from 64 bytes to 1500 bytes.

• Journal of the Korea Society of Computer and Information
• /
• v.20 no.9
• /
• pp.1-10
• /
• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.1
• /
• pp.147-156
• /
• 1998

In this paper, an arithmetic processor using multi-valued logic is designed. For implementing of multi-valued logic circuits, we use current-mode CMOS circuits and design encoder which change binary voltage-mode signals to multi-valued current-mode signals and decoder which change results of arithmetic to binary voltage-mode signals. To reduce the number of partial product we use 4-radix SD number partial product generation algorithm that is an extension of the modified Booth's algorithm. We demonstrate the effectiveness of the proposed arithmetic circuits through SPICE simulation and Hardware emulation using FPGA chip.