References
- S. Ozdemir, D. Sinha, G. Memik, J. Adams, and H. Zhou, "Yield-Aware Cache Architectures". In Proc. of IEEE/ACM Int'l Symposium on Microarchitecture, pp. 15-25, Dec. 2006.
- S. Ozdemir, A. Mallik, J. C. Ku, G. Memik, and Y. I. Ismail, "Variable latency caches for nanoscale processor". SC 2007, In Proc. of 2007 ACM/IEEE Conference on Supercomputing, pp. 1-10, Nov. 2007.
- M. Mutyam, F. Wang, K. Ramakrishnan, V. Narayanan, M. T. Kandemir, Y. Xie, and M. J. Irwin, "Process Variation-Aware Adaptive Cache Architecture and Management". IEEE Trans. Computers 58(7), pp. 865-877, Jul. 2009. https://doi.org/10.1109/TC.2009.30
- A. Agarwal, B. C. Paul, H. Mahmoodi. A. Datta, and K. Roy, "A process-tolerant cache architecture for improved yield in nanoscale technologies", IEEE Transaction on VLSI Systems, vol. 13, No. 1, pp. 27-38, Jan. 2005. https://doi.org/10.1109/TVLSI.2004.840407
- A. Agarwal, B. C. Paul, S. Mukhopadhyay, and K. Roy, "Process variation in embedded memories: failure analysis and variation aware architecture", IEEE Jnl. of Solid-State Circuits, vol. 40, Issue 9, Sep. 2005.
- Y. Pan, J. Kong, S. Ozdemir, G. Memik, and S. W. Chung, "Selective wordline voltage boosting for caches to manage yield under process variations". In Proc. of Design Automation Conference, pp. 57-62, Jul. 2009.
- J. Kong, Y. Pan, S. Ozdemir, A. Mohan, G. Memik, and S. W. Chung, "Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations". IEEE Trans. VLSI Syst. vol. 20, no. 8, pp. 1532-1536, Aug. 2012. https://doi.org/10.1109/TVLSI.2011.2159634
- M. Mutyam, and N. Vijaykrishnan, "Working with process variation aware caches". In Proc. of Design, Automation and Test in Europe, pp. 1152-1157, Mar. 2007.
- S. Ozdemir, Y. Pan, A. Das, G. Memik, G. H. Loh, and A. N. Choudhary, "Quantifying and coping with parametric variations in 3D-stacked microarchitectures". In Proc. of Design Automation Conference, pp. 144-149, Jun. 2010.
- J. Kong, and S. W. Chung, "Exploiting narrow-width values for process variation-tolerant 3-D microprocessors". In Proc. of Design Automation Conference, pp. 1197-1206, Jun. 2012.
- J. Kong, F. Koushanfar, and S. W. Chung, "An energy-efficient last-level cache architecture for process variation-tolerant 3D microprocessors". IEEE Trans. Computers, published online
- J. Tschanz, K. A. Bowman, and V. De. "Variation-tolerant circuits: circuit solutions and techniques". In Proc. of Design Automation Conference, pp. 762-763, Jun. 2005.
- J. Gregg and T. W. Chen. "Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well Adaptive Body Biasing (IWABB)". In Proc. of IEEE Int'l Symposium on Quality Electronic Design, Mar. 2007.
- R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas, "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing". In Proc. of IEEE/ACM Int'l Symposium on Microarchitecture, pp. 27-42, Dec. 2007.
- H. Li, Y. Chen, K. Roy, and C.-K. Koh, "SAVS: a self-adaptive variable supply-voltage technique for process-tolerant and power-efficient multi-issue superscalar processor design". In Proc. of Asia South Pacific Design Automation Conference, Jan. 2006.
- B. -S. Jung and J. -H. Lee, "Cache memory system for high performance CPU with 4GHz", Journal of The Korea Society of Computer and Information, Vol. 18, No. 2, pp. 1-8, Feb. 2013. https://doi.org/10.9708/jksci.2013.18.2.001
- N. R. Yang, J. M. Kim, and C. H. Kim, "Energy-aware Instruction Cache Design using Backward Branch Information for Embedded Processors", Journal of The Korea Society of Computer and Information, Vol. 13, No. 6, pp. 33-39, Nov. 2008.
- Y. -J. Park, J. -M. Kim, and C. H. Kim, "Low-power Filter Cache Design Technique for Multicore Processors", Journal of The Korea Society of Computer and Information, Vol. 14, No. 12, pp. 9-16, Dec. 2009.
-
Intel
$^{(R)}$ Atom$^{TM}$ Processor C2750 (4M Cache, 2.40 GHz), http://ark.intel.com/products/77987 - T. Carlson, W. Heirman, and L. Eeckhout. "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation". In Proc. of the 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC), pp. 1-12, Nov. 2011.
- S. Li, J.-H. Ahn, R. Strong, J. Brockman, D. Tullsen, and N. Jouppi. "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures". In Proc. of 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469-480, Dec. 2009.
- D. A. Patterson and J. L. Hennessy, "Computer Organization and Design The Hardware/Software Interface (ser. Comput. Architecture and Design), 4th edition". San Mateo, CA, USA: Morgan Kaufmann, 2012.