• 전자공학회논문지SC
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• 제40권6호
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• pp.78-86
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• 2003

텍스트 모드에서 흑백 데이터를 컬러 데이터로 변환시킬 때 하드웨어적인 방법을 이용하여 실시간적으로 변환할 수 있는 회로를 설계 및 구현하였다. Color Palette ROM에 화면을 구성하는 모든 페이지에 해당되는 색상 정보를 저장한다. 이 색상 정보는 8비트 단위로 출력이 되며 하위 4비트는 전경색, 상위 4비트는 배경색을 가지도록 지정한다. Address Reduction ROM을 두어 중복되는 어드레스를 배제하여 Color Palette ROM의 용량을 1/16로 감소시킬 수 있도록 하였으며, 다수 개의 D-FF을 두어 어드레스와 데이터 그리고 페이지 정보를 임시로 저장한 후에, Counter를 통해 실시간에 8회의 처리과정을 거친 후 Multiplex에서 전경색과 배경색을 구분하여 컬러 비디오 컨트롤러에 색상 정보를 보내도록 설계하였다. 기존의 흑백 LCD 디스플레이를 사용하고 있는 각종 제어장치 설비를 컬러로 변환함에 있어서 용이한 실시간 인터페이스로 활용될 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.184-193
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• 2015

This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our cost-efficient automatic large data acquisition method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.197-199
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• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• ETRI Journal
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• 제38권5호
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• pp.981-987
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• 2016

We present a cost-effective dual polarization quadrature phase-shift coherent receiver module using a silica planar lightwave circuit (PLC) hybrid assembly. Two polarization beam splitters and two $90^{\circ}$ optical hybrids are monolithically integrated in one silica PLC chip with an index contrast of $2%-{\Delta}$. Two four-channel spot-size converter integrated waveguide-photodetector (PD) arrays are bonded on PD carriers for transverse-electric/transverse-magnetic polarization, and butt-coupled to a polished facet of the PLC using a simple chip-to-chip bonding method. Instead of a ceramic sub-mount, a low-cost printed circuit board is applied in the module. A stepped CuW block is used to dissipate the heat generated from trans-impedance amplifiers and to vertically align RF transmission lines. The fabricated coherent receiver shows a 3-dB bandwidth of 26 GHz and a common mode rejection ratio of 16 dB at 22 GHz for a local oscillator optical input. A bit error rate of $8.3{\times}10^{-11}$ is achieved at a 112-Gbps back-to-back transmission with off-line digital signal processing.

• 대한전자공학회논문지SD
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• 제38권1호
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• pp.44-54
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• 2001

본 논문에서는 아날로그 회로에 존재하는 강고장(hard fault)과 약고장(soft fault)을 검출하기 위한 새로운 테스트 방식을 제안한다. 제안한 테스트 방식은 연산 증폭기의 특성중 하나인 오프셋 전압(offset voltage)을 이용한다. 테스트 시, 테스트 대상 회로(CUT: Circuit Under Test)는 귀환 루프를 가지는 단일 이득 연산 증폭기로 변환된다. 연산 증폭기의 입력이 접지되었을 때, 정상 회로는 작은 오프셋 전압을 가지지만 고장이 존재하는 회로는 큰 오프셋 전압을 가진다. 따라서 오프셋 전압의 허용 오차를 벗어나는 연산증폭기 내에 존재하는 고장들을 검출할 수 있다. 제안한 테스트 방식은 테스트 패턴 없이 단지 입력을 접지시키면 되므로 테스트 패턴을 생성하는 문제를 제거시킬 수 있어 테스트 시간과 비용이 감소한다. HSPICE 모의 실험을 통하여 본 논문에서 제안하는 방식을 단일 연산증폭기와 듀얼 슬롭(dual slope) A／D 변환기에 적용한 결과 높은 고장 검출율(fault coverage)을 얻었다.

• Journal of Power Electronics
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• 제15권1호
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• pp.146-159
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• 2015

Since the power capacity needed for the propulsion of large ships is very large, a multiphase AC induction propulsion mode is generally adopted to meet the higher requirements of reliability, redundancy and maintainability. This paper gives a detailed description of the development of a 20MW fifteen-phase PWM driver for advanced fifteen-phase propulsion induction motors with a special third-harmonic injection in terms of the main circuit hardware, control system design, experiments, etc. The adoption of the modular design method for the main circuit hardware design can make the enclosed mechanical structure simple and maintainable. It can also avoid the larger switch stresses caused by the multiple turn on of the IGBTs in conventional large-capacity converter systems. The use of the distributed controller design method based on a high-speed fiber-optic ring net for the control system can overcome such disadvantages as the poor reliability and long maintenance times arising from the conventional centralized controller which is designed according to point-to-point communication. Finally, the performance of the 20MW PWM driver is verified by experimentation on a new fifteen-phase induction propulsion motor.

• Journal of Power Electronics
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• 제14권3호
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• pp.444-457
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• 2014

This paper presents the design and realization of a digital PV simulator with a Push-Pull Forward (PPF) circuit based on the principle of modular hardware and configurable software. A PPF circuit is chosen as the main circuit to restrain the magnetic biasing of the core for a DC-DC converter and to reduce the spike of the turn-off voltage across every switch. Control and I/O interface based on a personal computer (PC) and multifunction data acquisition card, can conveniently achieve the data acquisition and configuration of the control algorithm and interface due to the abundant software resources of computers. In addition, the control program developed in Matlab/Simulink can conveniently construct and adjust both the models and parameters. It can also run in real-time under the external mode of Simulink by loading the modules of the Real-Time Windows Target. The mathematic models of the Push-Pull Forward circuit and the digital PV simulator are established in this paper by the state-space averaging method. The pole-zero cancellation technique is employed and then its controller parameters are systematically designed based on the performance analysis of the root loci of the closed current loop with $k_i$ and $R_L$ as variables. A fuzzy PI controller based on the Takagi-Sugeno fuzzy model is applied to regulate the controller parameters self-adaptively according to the change of $R_L$ and the operating point of the PV simulator to match the controller parameters with $R_L$. The stationary and dynamic performances of the PV simulator are tested by experiments, and the experimental results show that the PV simulator has the merits of a wide effective working range, high steady-state accuracy and good dynamic performances.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.459-462
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• 2010

본 논문은 근육의 기능을 조절하는 신경말단에 전기적인 자극을 가하여 신경의 반응 정도를 측정하는 플랫폼 구현에 관한 연구로써, 전기 자극에 대한 신경반응이 가해지는 전류량, 가해지는 전류지속시간, 전극위치에 따른 반응을 측정하였다. 신격자극의 전극 위치는 표면말달 운동신경이면 어느 신경이든지 가능하고, 신격자극 양식에는 단순연축자극(Single Twitch Stimulation), 사연속자극(Train-of-four, TOF), 두 집단 발사자극(Double Burst Stimulation, DBS)이 있다. 임베디드 시스템기반으로 가기위한 저전력 MCU를 선정하고, 기본적인 신경자극반응 측정 센서의 민감도를 알아보기 위해 센서 인터페이스를 구성하여 반응정도를 측정해야 한다. 그리고 측정된 Data의 정확도를 높이기 위해 고성능의 AD Convertor 선정하여 플랫폼을 구현하였다. 또한 본 논문의 플랫폼은 의료기기용으로 개발되었기 때문에 시스템 이용자의 안전을 고려하여 전원회로 구성 시 전원 Isolation를 고려하여 설계하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.392-395
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• 2003

For the purpose of digital x-ray imaging, many materials such as $PbI_2$, $HgI_2$, TlBr, CdTe and CdZnTe have been under development for servaral years as direct converter layer. $Hgl_2$ film detector have recently been shown as one of the most promising semiconductor materials to be used as direct converters in x-ray digital radiography. This paper, the $HgI_2$ films are deposited on conductive-coated glass by screen printing, in which $HgI_2$ powder is embedded in a binder and solvent, and the slurry is used to coat the conductive-coated glass. We investigated electrical characteristic of the fabricated $HgI_2$ films. The x-ray response to radiological x-ray generator of 70Kvp using the current integration mode will be reported for screen printing films. These results indicate that $HgI_2$ detectors have high potential as new digital x-ray imaging devices for radiography.