1 |
Fast EP-ROM 홈페이지, http://www.st.com
|
2 |
M. F. Tasi and H. C. Chen, 'Design and Impelmentation of a CPLD-Based SVPWM ASIC for Variable-Speed Control of AC Motor Drives', IEEE International Conference on, Power Electronics and Drive Systems, vol. 1, pp. 322-328, Jan., 2001
|
3 |
심수석, 'PWM 컬러 STN-LCD제어기 설계 및 FPGA구현', P.N.U., Feb., 1996
|
4 |
C. Yu and H. Yu, 'The design of general purpose parallel interface based on CPLD', IEEE 4th International Conference on, ASIC 2001, pp. 526-529, 2001
DOI
|
5 |
David VAN Bout, 'FPGA DESIGN 이론 및 실습', 홍릉과학출판사, 2000
|
6 |
이준성, 서강수, 'Xilinx Foundation을 이용한 디지털 시스템 설계', 복두출판사, 2001
|
7 |
W. Gunther, R. Drechsler, 'Performance driven optimization for MUX based FPGAs', IEEE 2001 Fourteenth International Conference on,VLSI Design, pp. 311-316, 2001
DOI
|
8 |
R. Bakalash, Xu. Zhong, 'A barrel shift microsystem for parallel processing', IEEE Proceedings of the 23rd Annual Workshop and Symposium., Micro programming and Microarchitecture. Micro 23. Workshop on, pp. 223-229, 1990
DOI
|
9 |
Ting Wu, Chi-Ying Tsui, M. Hamdi, 'A 2Gb/s 256*256 CMOS crossbar switch fabric core design using pipelined MUX', IEEE International Symposium on, ISCAS 2002,Circuits and Systems, vol. 2, pp. 568-571, 2002
|
10 |
Y. Fuji, J. O'Neill, P. Larsson, D. Inglis, J. Othmer, 'A 1.5V 86mW/ch 8-channel 622-3125Mb/s/ch CMOS serdes macrocell with selectable MUX/DEMUX ratio', IEEE 2002 International Solid-State Circuits Conference, Digest of Technical Papers, vol. 2, pp. 48-396, 2002
|