• 대한전자공학회논문지SD
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• 제41권5호
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• pp.71-80
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• 2004

본 논문은 mobile platform에서 사용될 Multimedia 적용을 위한 embedded Processor의 기본 구조 연구에 관한 내용으로 MPEG4 응용에 적합한 processor의 기본 구조 그리고 mobile platform에 적용될 수 있는 energy efficiency를 고려한 구조설계를 주 내용으로 하고 있다. multimedia 응용 embedded processor의 기본 구현 구조 요소인 processor data path architecture(pipeline, branch prediction, multiple issue superscalar, function unit number)의 기본 구조 설정과 cache hierarchy와 그 구성의 적합한 예상구조를 설정하기 위해 본 논문에서는 multimedia 응용 프로그램인 MPEG4를 processor simulator의 test bench로 사용하여 다양한 구조에 대한 simulation을 수행하였다. 그리고 mobile platform 적용에 적합한 구조인지에 대한 문제를 energy efficiency관점에서 고찰하여 적용 가능한 기본 processor 구조를 설정하였다. 그리고 본 논문에서 제안된 기본 구조 연구는 mobile platform에 바로 적용이 가능하며 더 나아가 특정 응용 프로그램에 최적의 성능을 발휘할 수 있는 자동화 설계기반환경에서의 configurable processor 설계에서 그 기본 processor 구조로 사용될 수 있다.

• 디지털산업정보학회논문지
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• 제4권1호
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• pp.9-16
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• 2008

This paper presents a frequency selection algorithm for minimization power consumption of processor in Mobile System. The proposed algorithm has processor designed low power processor using clock gating method. Clock gating method has improved the power dissipation by control main clock through the bus which is embedded clock block applying the method of clock gating. Proposed method has compared power consumption considered the dynamic power for processor, selected frequency has considered energy gain and energy consumption for designed processor. Or reduced power consumption with decreased processor speed using slack time. This technique has improved the life time of the mobile systems by clock gating method, considered energy and using slack time. As an results, the proposed algorithm reduce average power saving up to 4% comparing to not apply processor in mobile system.

• Current Optics and Photonics
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• 제2권5호
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• pp.453-459
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• 2018

We have developed a high-performance signal-processing and image-rendering heterogeneous computation system for optical coherence tomography (OCT) on mobile processor. In this paper, we reveal it by demonstrating real-time OCT image processing using a Snapdragon 800 mobile processor, with the introduction of a heterogeneous image visualization architecture (HIVA) to accelerate the signal-processing and image-visualization procedures. HIVA has been designed to maximize the computational performances of a mobile processor by using a native language compiler, which targets mobile processor, to directly access mobile-processor computing resources and the open computing language (OpenCL) for heterogeneous computation. The developed mobile image processing platform requires only 25 ms to produce an OCT image from $512{\times}1024$ OCT data. This is 617 times faster than the naïve approach without HIVA, which requires more than 15 s. The developed platform can produce 40 OCT images per second, to facilitate real-time mobile OCT image visualization. We believe this study would facilitate the development of portable diagnostic image visualization with medical imaging modality, which requires computationally expensive procedures, using a mobile processor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.917-920
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• 2005

This paper presents 3D graphics geometry processor for mobile applications. Geometry stage needs to cope with the large amount of computation. Geometry stage consists of transformation process and lighting process. To deal with computation in geometry stage, the vector processor that is based on pipeline chaining is proposed. The performance of proposed 3D graphics geometry processor is up to 4.3M vertex/sec at 100 MHz. Also, the designed processor is compliant with OpenGL ES that is widely used for standard API of embedded system. The proposed structure can be efficiently used in 3D graphics accelerator for mobile applications.

• 디지털산업정보학회논문지
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• 제8권1호
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• 전기학회논문지
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• 제63권1호
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• pp.85-91
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• 2014

As RFID is utilized more frequently and diversely in terms of its application areas, the application of mobile RFID technology, which integrates cellular networks and RFID, is highly anticipated. The growth and development of the RFID field has bolstered the development of mobile RFID chips to be embedded in mobile phones. Because mobile RFID chips are embedded in cell phones, limitations such as low power, small form factor, and costliness must be confronted. This study presents the design of a RFID digital baseband processor that is suitable for mobile readers. The RF analog component, which affects the baseband signals, is designed separately, in consideration of the limitations stated above. The function of the baseband processor was verified through simulations and prototyped using FPGA. The power consumption of the chip is 20mW under a 20MHz clock and the chip measures $3mm{\times}3mm$.

• 한국통신학회논문지
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• 제33권11A호
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• pp.1117-1123
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• 2008

모바일 멀티미디어 응용을 위한 기존의 프로세서들이 다방면에서 검증되고 응용되고 있다. 그런데, 이 모바일 멀티미디어 응용을 위해서 채택할 수 있는 하드 와이어드 즉 ASIC으로 된 칩 솔루션은 유연성이 떨어지며 비용이 많이 소요된다. 또한 유연성이 큰 CPU 솔루션은 그 성능에서 한계에 봉착하게 된다. 그러므로 ASIC 과 같은 성능과 CPU 같은 유연성 모두를 충족시키는 방법으로 재구성형 연산 프로세서를 사용하는 방법이 추천된다. 특히, 모바일 시스템들은 저전력과 고성능을 같이 추구하고 있으므로 본 논문에서는 이들을 모두 충족시키는 고에너지효율을 가지는 재구성형 프로세서를 제안한다. 130nm CMOS 기술에 의해 제작된 것은 121M0PS/mW의 에너지효율을 보이며 이를 90nm CMOS 기술과 명령어의 효율적인 사용을 통한 재구성형 프로세서의 시뮬레이션 결과는 539MOPS/mW의 에너지효율을 보임을 확인하였다. 또한 그 응용을 MP3의 IMDCT와 MPEG4의 DF H.264의 ME 알고리즘에 대해 시행함으로써 모바일 멀티미디어 분야에 적용될 수 있음을 보였다.

• 한국인터넷방송통신학회논문지
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• 제10권2호
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• pp.97-102
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• 2010

본 논문에서는 IEEE 802.16e mobile WiMax 시스템을 위한 효율적인 FFT 프로세서 구조를 제안한다. 제안된 scalable FFT/IFFT 프로세서는 128/512/1024/2048-point FFT 연산을 가변적으로 수행할 수 있다. 또한 mixed radix (MR) 기법과 multi- path delay commutator (MDC) 구조를 사용하여 비단순 승산을 줄임으로써 기존의 설계 구조에 비해 시스템 수율 변화 없이 하드웨어 복잡도를 크게 감소시켰다. 제안된 scalable FFT/IFFT 프로세서는 하드웨어 설계 언어 (HDL)를 이용하여 설계 되었고, 0.18um CMOS 스탠다드 셀 라이브러리를 이용하여 논리 합성되었다. 논리 합성 결과 4채널 radix-2 MDC (R2MDC) FFT 프로세서와 비교시 16% 감소된 게이트 수와 27% 감소된 메모리로 구현 가능함이 확인되었다.

• International journal of advanced smart convergence
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• 제8권1호
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• pp.9-17
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• 2019

In this article, we present a performance enhancement scheme for mobile applications by adopting persistent memory. The proposed scheme supports the deadline guarantee of real-time applications like a video player, and also provides reasonable performances for non-real-time applications. To do so, we analyze the program execution path of mobile software platforms and find two sources of unpredictable time delays that make the deadline-guarantee of real-time applications difficult. The first is the irregular activation of garbage collection in flash storage and the second is the blocking and time-slice based scheduling used in mobile platforms. We resolve these two issues by adopting high performance persistent memory as the storage of real-time applications. By maintaining real-time applications and their data in persistent memory, I/O latency can become predictable because persistent memory does not need garbage collection. Also, we present a new scheduler that exclusively allocates a processor core to a real-time application. Although processor cycles can be wasted while a real-time application performs I/O, we depict that the processor utilization is not degraded significantly due to the acceleration of I/O by adopting persistent memory. Simulation experiments show that the proposed scheme improves the deadline misses of real-time applications by 90% in comparison with the legacy I/O scheme used in mobile systems.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.246-247
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• 2008

Further evolutions of technologies and needs of users will make mobile equipments improved. To make this happen, processor's good performance is essential. Hence, This paper propose a reform of Instruction Execute and Instruction Decode of contemporary ARMv7 which needs low-power and has the high performance for a faster processor. The first chapter explains why the performance of a processor has to be upgraded, the second chapter shows current technologies. The third chapter explains about the proposal and illustrates the structure. Finally, in the forth chapter, the conclusion will be made. 3-way Superscalar, that is proposed in this paper, will make designing a faster processor possible. And it will contribute for the advanced performance of mobile equipments.